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PDF CY7C199N Data sheet ( Hoja de datos )
| Número de pieza | CY7C199N | |
| Descripción | 32 K x 8 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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32 K × 8 Static RAM
Features
■ High speed
❐ 15 ns
■ Fast tDOE
■ CMOS for optimum speed/power
■ Low active power
❐ 550 mW (max, 15 ns “L” version)
■ Low standby power
❐ 0.275 mW (max, “L” version)
■ 2 V data retention (“L” version only)
■ Easy memory expansion with CE and OE features
■ TTL-compatible inputs and outputs
■ Automatic power-down when deselected
Logic Block Diagram
CY7C199N
32 K × 8 Static RAM
Functional Description
The CY7C199N is a high-performance CMOS static RAM
organized as 32,768 words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE) and active LOW
Output Enable (OE) and three-state drivers. This device has an
automatic power-down feature, reducing the power consumption
by 81% when deselected. The CY7C199N is in the standard
300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location addressed
by the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device and
enabling the outputs, CE and OE active LOW, while WE remains
inactive or HIGH. Under these conditions, the contents of the
location addressed by the information on address pins are
present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable (WE)
is HIGH. A die coat is used to improve alpha immunity.
For a complete list of related documentation, click here.
AAAAAAAAAA1234567890
CE
WE
OE
INPUT BUFFER
1024 x 32 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-06493 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 18, 2014
1 page  
CY7C199N
Capacitance
Parameter [3]
Description
CIN
COUT
Input capacitance
Output capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 5.0 V
Max Unit
8 pF
8 pF
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [4]
5V
OUTPUT
R1 481
5V
OUTPUT
R1 481
30 pF
INCLUDING
JIG AND
SCOPE
R2
255
(a)
5 pF R2
255
INCLUDING
JIG AND
SCOPE (b)
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
167
1.73 V
3.0 V
GND
10%
tr
ALL INPUT PULSES
90%
90%
10%
tr
Data Retention Characteristics
Over the Operating Range (L-version only)
Parameter
VDR
ICCDR
tCDR[3]
tR [4]
Description
VCC for Data Retention
Data Retention Current
L
Chip Deselect to Data Retention Time
Operation Recovery Time
Conditions [5]
VCC = VDR = 2.0 V,
CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or
VIN < 0.3 V
Min Max Unit
2.0 – V
– 10 A
0 – ns
200 – s
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC
3.0 V
VDR > 2 V
tCDR
CE
3.0 V
tR
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. tR< 3 ns for -15 speed.
5. No input may exceed VCC + 0.5 V.
Document Number: 001-06493 Rev. *E
Page 5 of 14
5 Page 
CY7C199N
Package Diagrams
Figure 9. 28-pin TSOP 1 (8 × 13.4 × 1.2 mm) Package Outline, 51-85071
51-85071 *J
Document Number: 001-06493 Rev. *E
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CY7C199N.PDF ] | |
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