CY7C107D PDF даташит
Спецификация CY7C107D изготовлена «Cypress Semiconductor» и имеет функцию, называемую «1-Mbit (1 M x 1) Static RAM». |
|
Детали детали
Номер произв | CY7C107D |
Описание | 1-Mbit (1 M x 1) Static RAM |
Производители | Cypress Semiconductor |
логотип |
15 Pages
No Preview Available ! |
CY7C107D
CY7C1007D
1-Mbit (1 M × 1) Static RAM
1-Mbit (1 M × 1) Static RAM
Features
■ Pin- and function-compatible with CY7C107B/CY7C1007B
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 80 mA @ 10 ns
■ Low complementary metal oxide semiconductor (CMOS)
standby power
❐ ISB2 = 3 mA
■ 2.0 V data retention
■ Automatic power-down when deselected
■ CMOS for optimum speed/power
■ Transistor transistor logic (TTL) compatible inputs and outputs
■ CY7C107D available in Pb-free 28-pin 400-Mil wide Molded
SOJ package. CY7C1007D available in Pb-free 28-pin 300-Mil
wide Molded SOJ package
Functional Description
The CY7C107D [1] and CY7C1007D [1] are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit. Easy
memory expansion is provided by an active LOW Chip Enable
(CE) and tri-state drivers. These devices have an automatic
power-down feature that reduces power consumption by more
than 65% when deselected. The output pin (DOUT) is placed in a
high-impedance state when:
■ Deselected (CE HIGH)
■ When the write operation is active (CE and WE LOW)
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the input pin (DIN) is written into the
memory location specified on the address pins (A0 through A19).
Read from the device by taking Chip Enable (CE) LOW while
while forcing Write Enable (WE) HIGH. Under these conditions,
the contents of the memory location specified by the address
pins appears on the data output (DOUT) pin.
The CY7C107D and CY7C1007D devices are suitable for
interfacing with processors that have TTL I/P levels. It is not
suitable for processors that require CMOS I/P levels. Please see
Electrical Characteristics on page 4 for more details and
suggested alternatives.
For a complete list of related documentation, click here.
Logic Block Diagram
DIN
A0
A1
A2
A3
A4
A5
A6
A7
A8
CE
WE
INPUT BUFFER
1M x 1
ARRAY
DOUT
COLUMN DECODER
POWER
DOWN
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05469 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 24, 2014
No Preview Available ! |
CY7C107D
CY7C1007D
Contents
Pin Configuration ............................................................. 3
Selection Guide ................................................................ 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 10
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagrams .......................................................... 11
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC® Solutions ...................................................... 15
Cypress Developer Community ................................. 15
Technical Support ..................................................... 15
Document Number: 38-05469 Rev. *K
Page 2 of 15
No Preview Available ! |
Pin Configuration
Figure 1. 28-pin SOJ pinout (Top View) [2]
A10
A11
A12
A13
A14
A15
NC
A16
A17
AA1198
DOUT
WE
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 A9
26 A8
25 A7
24 A6
23 A5
22 A4
21 NC
20 A3
19 A2
18 A1
17 A0
16 DIN
15 CE
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current, ISB2
Description
CY7C107D
CY7C1007D
CY7C107D-10
CY7C1007D-10
10
80
3
Unit
ns
mA
mA
Note
2. NC pins are not connected on the die.
Document Number: 38-05469 Rev. *K
Page 3 of 15
Скачать PDF:
[ CY7C107D.PDF Даташит ]
Номер в каталоге | Описание | Производители |
CY7C107 | (CY7C107 / CY7C1007) 1M x 1 Static RAM | Cypress Semiconductor |
CY7C1071DV33 | 32-Mbit (2M x 16) Static RAM | Cypress Semiconductor |
CY7C1079DV33 | 32-Mbit (4 M x 8) Static RAM | Cypress Semiconductor |
CY7C107B | 1M x 1 Static RAM | Cypress Semiconductor |
Номер в каталоге | Описание | Производители |
TL431 | 100 мА, регулируемый прецизионный шунтирующий регулятор |
Unisonic Technologies |
IRF840 | 8 А, 500 В, N-канальный МОП-транзистор |
Vishay |
LM317 | Линейный стабилизатор напряжения, 1,5 А |
STMicroelectronics |
DataSheet26.com | 2020 | Контакты | Поиск |