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PDF ADP5043 Data sheet ( Hoja de datos )
| Número de pieza | ADP5043 | |
| Descripción | Micro PMU | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Micro PMU with 800 mA Buck, 300 mA LDO,
Supervisory, Watchdog, and Manual Reset
ADP5043
FEATURES
GENERAL DESCRIPTION
Input voltage range: 2.3 V to 5.5 V
One 800 mA buck regulator
One 300 mA LDO
20-lead, 4 mm × 4 mm LFCSP package
Initial regulator accuracy: ±1%
Overcurrent and thermal protection
Soft start
Undervoltage lockout
Open-drain processor reset with threshold monitoring
±1.5% threshold accuracy over the full temperate range
Guaranteed reset output valid to VCC = 1 V
Dual watchdog for secure systems
Watchdog 1 controls reset
Watchdog 2 controls reset and regulators power cycle
Buck regulator key specifications
Current-mode topology for excellent transient response
3 MHz operating frequency
Uses tiny multilayer inductors and capacitors
Mode pin selects forced PWM or auto PFM/PSM modes
100% duty cycle low dropout mode
LDO key specifications
Low VIN from 1.7 V to 5.5 V
Stable with1 µF ceramic output capacitors
High PSRR, 60 dB up to 1 kHz/10 kHz
Low output noise
Low dropout voltage: 150 mV at 300 mA load
−40°C to +125°C junction temperature range
The ADP5043 combines one high performance buck regulator
and one low dropout regulator (LDO) in a small 20-lead LFCSP
to meet demanding performance and board space requirements.
The high switching frequency of the buck regulator enables use
of tiny multilayer external components and minimizes board space.
The MODE pin selects the buck’s mode of operation. When set
to logic high, the buck regulator operates in forced PWM mode.
When the MODE pin is set to logic low, the buck regulator
operates in PWM mode when the load is around the nominal
value. When the load current falls below a predefined threshold,
the regulator operates in power save mode (PSM) improving
the light-load efficiency.
The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP5043 LDO extend the battery life of
portable devices. The LDO maintains a power supply rejection
of greater than 60 dB for frequencies as high as 10 kHz while
operating with a low headroom voltage.
Each regulator is activated by a high level on the respective
enable pin. The ADP5043 is available with factory programmable
default output voltages and can be set to a wide range of options.
The ADP5043 contains supervisory circuits that monitor
power supply voltage levels and code execution integrity in
microprocessor-based systems. The ADP5043 also provides
power-on reset signals. An on-chip dual watchdog timer can
reset the microprocessor or power cycle the system (Watchdog 2)
if it fails to strobe within a preset timeout period.
HIGH LEVEL BLOCK DIAGRAM
VIN1 = 2.3V
TO 5.5V
RFILT
30Ω
C5
4.7µF
ON
OFF
AVIN
VIN1
EN1
VIN2 = 1.7V
TO 5.5V
C1
1µF
VIN2
ON
OFF
EN2
AVIN
ADP5043
BUCK
EN_BK
LDO
EN_LDO
SW
VOUT1
PGND
L1
1µH
VOUT1 @
C6 800mA
10µF
MODE
VOUT2
FPWM
PSM/PWM
VOUT2 @
300mA
C2
1µF
AVIN
WSTAT
MR nRSTO
NC WDI1
WDI2
NC
WMOD
GND
AGND GND
VIN
WD1 MODE
SELECTION
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
1 page  
ADP5043
Parameter
Watchdog 2 Timeout Period (tWD2)
Option A
Option B
Option C
Option D
Option E
Option F
Option G
Option H
Watchdog 2 Power Off Period (tPOFF)
Option A
Option B
WDI1 Pulse Width
WDI2 Pulse Width
Watchdog Status Timeout Period (tWDCLEAR)
WDI1 Input Current (Source)
WDI1 Input Current (Sink)
WDI2 Internal Pull-Down
MANUAL RESET INPUT
MR Input Pulse Width
MR Glitch Rejection
MR Pull-Up Resistance
MR to Reset Delay
Min Typ Max
6 7.5 9
Watchdog 2 disabled
3.2 4 4.8
6.4 8 9.6
11.2 16 19.2
25.6 32 38.4
51.2 64 76.8
102.4
128 153.8
210
400
80
8
11.2
8 15 20
−30 −25 −14
45
1
220
25 52 80
280
Data Sheet
Unit Test Conditions/Comments
sec
min
min
min
min
min
min
ms
ms
ns VIL = 0.4 V, VIH = 1.2 V
µs VIL = 0.4 V, VIH = 1.2 V
sec
µA VWDI1 = VCC, time average
µA VWDI1 = 0, time average
kΩ
µs
ns
kΩ
ns VCC = 5 V
Rev. A | Page 4 of 32
5 Page 
ADP5043
1.797
1.796
1.795
1.794
1.793
1.792
VIN = 5.5V
VIN = 4.5V
VIN = 3.6V
1.791
1.790
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
OUTPUT CURRENT (A)
Figure 9. Buck Load Regulation Across Input Voltage, VOUT1 = 1.8 V,
PWM Mode
100
90
80
70
60
50
40
30
20
10
0
0.0001
0.001
0.01
3.6V
4.5V
5.5V
0.1 1
OUTPUT CURRENT (A)
Figure 10. Buck Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 3.3 V, Auto Mode
100
3.6V
90 4.5V
5.5V
80
70
60
50
40
30
20
10
0
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
Figure 11. Buck Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 3.3 V, PWM Mode
Data Sheet
100
90
80
70
60
50
40
30
20
2.4V
10
3.6V
4.5V
5.5V
0
0.0001
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
Figure 12. Buck Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 1.8 V, Auto Mode
100
2.4V
90
3.6V
4.5V
5.5V
80
70
60
50
40
30
20
10
0
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
Figure 13. Buck Efficiency vs. Load Current, Across Input Voltage,
VOUT1= 1.8 V, PWM Mode
100
–40°C
90 +25°C
+85°C
80
70
60
50
40
30
20
10
0
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
Figure 14. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 1.8 V,
PWM Mode
Rev. A | Page 10 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP5043.PDF ] | |
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