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PDF AD5592R Data sheet ( Hoja de datos )
| Número de pieza | AD5592R | |
| Descripción | 8-Channel 12-Bit Configurable ADC/DAC | |
| Fabricantes | Analog Devices | |
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Data Sheet
8-Channel, 12-Bit, Configurable ADC/DAC
with On-Chip Reference, SPI Interface
AD5592R
FEATURES
8-channel, configurable ADC/DAC/GPIO
Configurable as any combination of
8 × 12-bit DAC channels
8 × 12-bit ADC channels
8 × general-purpose digital input/output pins
Integrated temperature sensor
SPI interface
Available in
16-ball, 2 mm × 2 mm WLCSP
16-lead, 3 mm × 3 mm LFCSP
16-lead TSSOP
APPLICATIONS
Control and monitoring
General-purpose analog and digital inputs/outputs
GENERAL DESCRIPTION
The AD5592R/AD5592R-1 have eight I/Ox pins (I/O0 to I/O7)
that can be independently configured as digital-to-analog
converter (DAC) outputs, analog-to-digital converter (ADC)
inputs, digital outputs, or digital inputs. When an I/Ox pin is
configured as an analog output, it is driven by a 12-bit DAC.
The output range of the DAC is 0 V to VREF or 0 V to 2 × VREF.
When an I/Ox pin is configured as an analog input, it is
connected to a 12-bit ADC via an analog multiplexer. The input
range of the ADC is 0 V to VREF or 0 V to 2 × VREF. The ADC
has a total throughput rate of 400 kSPS. The I/Ox pins can also
be configured as digital, general-purpose input or output
(GPIO) pins. The state of the GPIO pins can be set or read back
by accessing the GPIO write data register or the GPIO read
configuration register, respectively, via a serial peripheral
interface (SPI) write or read operation.
The AD5592R/AD5592R-1 have an integrated 2.5 V, 25 ppm/°C
reference, which is turned off by default, and an integrated
temperature indicator, which gives an indication of the die
temperature. The temperature value is read back as part of an
ADC read sequence.
The AD5592R/AD5592R-1 are available in 16-ball, 2 mm ×
2 mm WLCSP, 16-lead, 3 mm × 3 mm LFCSP, and 16-lead
TSSOP. The AD5592R/AD5592R-1 operate over a temperature
range of −40°C to +105°C.
Table 1. Related Products
Part No. Description
AD5593R
AD5592R equivalent with VLOGIC and RESET pins and
an I2C interface
SYNC
SCLK
SDI
SDO
RESET
AD5592R
POWER-ON
RESET
FUNCTIONAL BLOCK DIAGRAM
VDD
VREF
INPUT
REGISTER
DAC
REGISTER
DAC 0
2.5V
REFERENCE
GPIO0
SPI
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
DAC 7
SEQUENCER
TEMPERATURE
INDICATOR
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
GPIO7
MUX
GND
Figure 1. AD5592R Functional Block Diagram
I/O0
I/O7
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD5592R
Data Sheet
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, VREF = 2.5 V (external), RL = 2 kΩ to GND, CL = 200 pF to GND, TA = TMIN to TMAX, temperature range = −40°C to +105°C,
unless otherwise noted.
Table 2.
Parameter
ADC PERFORMANCE
Resolution
Input Range
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset Error
Gain Error
Throughput Rate2
Track Time (tTRACK)2
Conversion Time (tCONV)2
Signal-to-Noise Ratio (SNR)
Min
0
0
−2
−1
500
Signal-to-Noise-and-Distortion (SINAD) Ratio
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Aperture Delay2
Aperture Jitter2
Channel-to-Channel Isolation
Input Capacitance
Full Power Bandwidth
DAC PERFORMANCE3
Resolution
Output Range
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset Error
Offset Error Drift2
Gain Error
Zero Code Error
Total Unadjusted Error
Capacitive Load Stability2
Resistive Load
Short-Circuit Current
0
0
−1
−1
−3
1
Typ Max
12
VREF
2 × VREF
+2
+1
±5
0.3
400
2
69
67
61
69
67
60
−91
−89
−72
91
91
72
15
12
50
−95
45
8.2
1.6
12
8
0.65
±0.03
±0.015
VREF
2 × VREF
+1
+1
+3
±0.2
±0.1
2
±0.25
±0.1
2
10
25
Unit1
Bits
V
V
LSB
LSB
mV
% FSR
kSPS
ns
µs
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
ns
ns
ps
dB
pF
MHz
MHz
Test Conditions/Comments
fIN = 10 kHz sine wave
When using the internal ADC buffer, there is
a dead band of 0 V to 5 mV
VDD = 2.7 V, input range = 0 V to VREF
VDD = 5.5 V, input range = 0 V to VREF
VDD = 5.5 V, input range = 0 V to 2 × VREF
VDD = 2.7 V, input range = 0 V to VREF
VDD = 3.3 V, input range = 0 V to VREF
VDD = 5.5 V, input range = 0 V to 2 × VREF
VDD = 2.7 V, input range = 0 V to VREF
VDD = 3.3 V, input range = 0 V to VREF
VDD = 5.5 V, input range = 0 V to 2 × VREF
VDD = 2.7 V, input range = 0 V to VREF
VDD = 3.3 V, input range = 0 V to VREF
VDD = 5.5 V, input range = 0 V to 2 × VREF
VDD = 3 V
VDD = 5 V
fIN = 5 kHz
At 3 dB
At 0.1 dB
Bits
V
V
LSB
LSB
mV
µV/°C
% FSR
% FSR
mV
% FSR
nF
nF
kΩ
mA
Output range = 0 V to VREF
Output range = 0 V to 2 × VREF
Output range = 0 V to VREF
Output range = 0 V to 2 × VREF
RLOAD = ∞
RLOAD = 1 kΩ
Rev. C | Page 4 of 42
5 Page 
AD5592R
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
BALL A1
INDICATOR
1 234
SDI SCLK RESET SYNC
A
GND I/O7 I/O0 VDD
B
I/O6 I/O3 I/O2 I/O1
C
I/O4 SDO VREF I/O5
D
AD5592R
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
Figure 5. AD5592R 16-Ball WLCSP Pin Configuration
Data Sheet
Table 7. AD5592R 16-Ball WLCSP Pin Function Descriptions
Pin No.
Mnemonic Description
A1 SDI Data In. Logic input. Data that is to be written to the DACs and control registers is provided on this input and
is clocked into the register on the falling edge of SCLK.
A2
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz when writing to the DACs. SCLK has a maximum speed of
20 MHz when performing a conversion or clocking data from the AD5592R.
A3
RESET
Asynchronous Reset Pin. Tie this pin high for normal operation. When this pin is brought low, the AD5592R is
reset to its default configuration.
A4
SYNC
Synchronization. Active low control input. SYNC is the frame synchronization signal for the input data.
When SYNC goes low, data is transferred in on the falling edges of the next 16 clocks.
B1 GND Ground Reference Point for All Circuitry on the AD5592R.
B2 I/O7 Input/Output 7. This pin can be configured as a DAC, ADC, or general-purpose digital input or output. The
function of this pin is determined by programming the I/Ox pin configuration registers (see Table 15 and
Table 16). I/O7 can also be configured as a BUSY signal to indicate when an ADC conversion is taking place
(see Table 30 and Table 31).
B3, C4, C3, C2,
D1, D4, C1
I/O0 to I/O6 Input/Output 0 Through Input/Output 6. These pins can be independently configured as DACs, ADCs, or
general-purpose digital inputs or outputs. The function of each pin is determined by programming the I/Ox
pin configuration registers (see Table 15 and Table 16).
B4 VDD Power Supply Input. The AD5592R operates from 2.7 V to 5.5 V, and this pin must be decoupled with a 0.1 µF
capacitor to GND.
D2 SDO Data Out. Logic output. The conversion results from the ADC, register reads, and temperature sensor
information are provided on this output as a serial data stream. The bits are clocked out on the rising edge
of the SCLK input. The MSB is placed on the SDO pin on the falling edge of SYNC. Because the SCLK can idle
high or low, the next bit is clocked out on the first rising edge of SCLK that follows a falling edge SCLK
while SYNC is low (see Figure 4).
D3 VREF Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on
this pin. A 0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the specified
performance from the AD5592R. When the internal reference is disabled, an external reference must be
applied to this pin. The voltage range for the external reference is 1 V to VDD.
Rev. C | Page 10 of 42
11 Page | ||
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| PDF Descargar | [ Datasheet AD5592R.PDF ] | |
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