PDF MG82FE308 Data sheet ( Hoja de datos )

Número de pieza	MG82FE308
Descripción	8051-Based MCU
Fabricantes	Megawin
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No Preview Available ! 8051-Based MCU MG82FE(L)308/316 Data Sheet Version: A1.0 This document contains information on a new product under development by Megawin. Megawin reserves the right to change or discontinue this product without notice.  Megawin Technology Co., Ltd. 2012 All rights reserved. 2013/11 version A1.0 1 page Content Features ............................................................................................................ 3 Content.............................................................................................................. 5 1. General Description .................................................................................... 7 2. Block Diagram ............................................................................................ 8 3. Special Function Register ........................................................................... 9 3.1. SFR Map.............................................................................................................................9 3.2. SFR Bit Assignment ..........................................................................................................10 3.3. SFR Paging.......................................................................................................................11 4. Pin Configurations..................................................................................... 12 4.1. Package Instruction...........................................................................................................12 MG82FE(L)308AD48.................................................................................................................12 4.2. Pin Description ..................................................................................................................14 5. System Clock............................................................................................ 15 5.1. Clock Structure..................................................................................................................15 5.2. Clock Register...................................................................................................................15 6. 8051 CPU Function Description................................................................ 17 6.1. CPU Register ....................................................................................................................17 6.2. CPU Timing.......................................................................................................................18 6.3. CPU Addressing Mode......................................................................................................18 7. Memory Organization................................................................................ 19 7.1. On-Chip Program Flash ....................................................................................................19 7.2. On-Chip Data RAM ...........................................................................................................20 7.3. On-chip expanded RAM (XRAM) ......................................................................................20 7.4. Declaration Identifiers in a C51-Compiler ..........................................................................22 8. Dual Data Pointer Register (DPTR) .......................................................... 23 9. Configurable I/O Ports .............................................................................. 24 9.1. IO Structure.......................................................................................................................24 9.1.1. Quasi-Bidirectional IO Structure..................................................................................24 9.1.2. Push-Pull Output Structure .........................................................................................25 9.1.3. Input-Only (High Impedance Input) Structure ..............................................................25 9.1.4. Open-Drain Output Structure ......................................................................................26 9.2. I/O Port Register ...............................................................................................................26 9.2.1. Port 0 Register............................................................................................................27 9.2.2. Port 1 Register............................................................................................................27 9.2.3. Port 2 Register............................................................................................................27 9.2.4. Port 3 Register............................................................................................................28 9.2.5. Port 4 Register............................................................................................................28 9.2.6. Port 5 Register............................................................................................................29 9.2.7. Port 6 Register............................................................................................................29 9.2.8. Port 7 Register............................................................................................................30 9.3. GPIO Sample Code ..........................................................................................................31 10. Interrupt .................................................................................................... 32 10.1.Interrupt Structure .............................................................................................................32 10.2.Interrupt Register ..............................................................................................................33 10.3.Interrupt Sample Code ......................................................................................................39 11. Timers/Counters ....................................................................................... 40 11.1.Timer0 and Timer1............................................................................................................40 11.1.1. Mode 0 Structure ........................................................................................................40 11.1.2. Mode 1 Structure ........................................................................................................41 11.1.3. Mode 2 Structure ........................................................................................................41 11.1.4. Mode 3 Structure ........................................................................................................42 MEGAWIN MG82FEL308_316 Data Sheet 5 5 Page High IFADRL ISP Flash Address Low E4H 00000000B IFMT ISP Mode Table E5H -- -- -- -- MS3 MS2 MS1 MS0 xxxx0000B IAPLB IAP Low Boundary Note 1 IAPLB6 IAPLB5 IAPLB4 IAPLB3 IAPLB2 IAPLB1 IAPLB0 -- 11111111B SCMD ISP Serial Command E6H xxxxxxxxB ISPCR ISP Control Register E7H ISPEN BS SRST CFAIL -- -- -- -- 0000xxxxB P4 Port 4 E8H -- P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 11111111B CCAP0L PWM Counter L-Duty EAH 00000000B B B Register F0H F7H F6H F5H F4H F3H F2H F1H F0H 00000000B P5 Port 5 F8H P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 11111111B CCAP0H PWM Counter H-Duty FAH 00000000B Note1: The registers are addressed by IFMT and SCMD. Please refer the IFMT register description for more detail information. 3.3. SFR Paging The MG82FE(L)308/316 features SFR paging, allowing the device to map many SFRs into the 0x80 to 0xFF memory address space. The SFR memory space has 16 pages. In this way, each memory location from 0x80 to 0xFF can access up to 128 SFRs. The MG82FE(L)308/316 utilizes two SFR pages: 0 and F. SFR pages are selected using the Special Function Register Page Index register, SFRPI. The procedure for reading and writing an SFR is as follows: 1. Select the appropriate SFR page number using the SFRPI register. 2. Use direct accessing mode to read or write the special function register (MOV instruction). SFRPI: SFR Page Index Register SFR Address = 0xAC SFR Page = All 765 -- -- -- RRR Reset Value = XXXX-0000 432 -- PIDX3 PIDX2 R R/W R/W Bit 7~4: Reserved for testing. Must write “0” on these bits. Bit 3~0: SFR Page Index. The available pages are only page “0” and “F”. 1 PIDX1 R/W 0 PIDX0 R/W PIDX[3:0] 0000 0001 0010 0011 …… …… …… 1111 Selected Page Page 0 Page 1 Page 2 Page 3 …… …… …… Page F There are two registers in Page 0 only, T2CON(C8H) and CCON(D8H), and two registers in Page F only, P6(C8H) and P7(D8H). Other registers are accessed in both page “0” and page “F”. MEGAWIN MG82FEL308_316 Data Sheet 11 11 Page

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