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ADF41020 Datasheet PDF Download - Analog Devices

Номер произв ADF41020
Описание 18 GHz Microwave PLL Synthesizer
Производители Analog Devices
логотип Analog Devices логотип 
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ADF41020 Даташит, Описание, Даташиты
Data Sheet
18 GHz Microwave PLL Synthesizer
ADF41020
FEATURES
18 GHz maximum RF input frequency
Integrated SiGe prescaler
Software compatible with the ADF4106/ADF4107/ADF4108
family of PLLs
2.85 V to 3.15 V PLL power supply
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
4000 V HBM/1500 V CDM ESD performance
APPLICATIONS
Microwave point-to-point/multipoint radios
Wireless infrastructure
VSAT radios
Test equipment
Instrumentation
GENERAL DESCRIPTION
The ADF41020 frequency synthesizer can be used to implement
local oscillators as high as 18 GHz in the up conversion and
down conversion sections of wireless receivers and transmitters.
It consists of a low noise, digital phase frequency detector
(PFD), a precision charge pump, a programmable reference
divider, and high frequency programmable feedback dividers
(A, B, and P). A complete phase-locked loop (PLL) can be
implemented if the synthesizer is used with an external loop
filter and voltage controlled oscillator (VCO). The synthesizer
can be used to drive external microwave VCOs via an active
loop filter. Its very high bandwidth means a frequency doubler
stage can be eliminated, simplifying system architecture and
reducing cost. The ADF41020 is software-compatible with the
existing ADF4106/ADF4107/ADF4108 family of devices from
Analog Devices, Inc. Their pinouts match very closely with
the exception of the ADF41020’s single-ended RF input pin,
meaning only a minor layout change is required when updating
current designs.
REFIN
AVDD DVDD
FUNCTIONAL BLOCK DIAGRAM
VP GND
R COUNTER
PHASE
FREQUENCY
DETECTOR
REFERENCE
RSET
CHARGE
PUMP
CP
CLK
DATA
LE
24-BIT INPUT
REGISTER
R COUNTER
LATCH
FUNCTION
LATCH
A, B COUNTER
LATCH
RFIN
3pF
50Ω
N = 4(BP + A)
DIVIDE
BY 4
P/P+ 1
A AND B
COUNTERS
LOCK
DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
AVDD
SDOUT
MUX
HIGH-Z
MUXOUT
M3 M2 M1
ADF41020
GND
CE
GND
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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ADF41020 Даташит, Описание, Даташиты
ADF41020
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 8
Reference Input Section............................................................... 8
REVISION HISTORY
1/14—Rev. A to Rev. B
Changes to Figure 6.......................................................................... 7
11/13—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Absolute Maximum Ratings Section and Table 3.... 5
10/12—Revision 0: Initial Version
Data Sheet
RF Input Stage................................................................................8
Prescaler..........................................................................................8
A Counter and B Counter ............................................................8
R Counter .......................................................................................9
PFD and Charge Pump.................................................................9
MUXOUT and Lock Detect.........................................................9
Input Shift Register .......................................................................9
The Function Latch.................................................................... 13
Applications Information .............................................................. 15
Interfacing ................................................................................... 15
PCB Design Guidelines ............................................................. 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
Rev. B | Page 2 of 16
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ADF41020 Даташит, Описание, Даташиты
Data Sheet
ADF41020
SPECIFICATIONS
DVDD = AVDD = VP = 3.0 V ± 5%, GND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted.
Table 1.
Parameter
RF CHARACTERISTICS
RF Input Frequency (RFIN)
RF Input Sensitivity
Maximum Allowable Prescaler
Output Frequency1
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency2
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET
ICP Three-State Leakage
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
Min
4.0
−10
10
0.8
5.1
1.4
1.4
Typ
5.0
625
3
5.1
1
2
1
2
VOH, Output High Voltage
IOH, Output High Current
VOL, Output Low Voltage
IOL, Output Low Current
POWER SUPPLIES
AVDD
DVDD
VP
IDD3
IP3
Power-Down Mode
DVDD − 0.4
2.85
2.85
2.85
27
4.5
1
Max Unit
18.0 GHz
+10 dBm
350 MHz
Test Conditions/Comments
See Figure 1 for input circuit
400
DVDD
10
±100
MHz
V p-p
pF
µA
100 MHz
mA
µA
%
5.1 kΩ
2 nA
%
%
%
V
0.6 V
±1 µA
10 pF
V
V
500 µA
0.4 V
500 µA
3.15 V
3.15 V
3.15 V
30 mA
5 mA
µA
For f < 10 MHz, ensure slew rate > 50 V/μs
Biased at DVDD/2 when input is ac-coupled
Programmable, see Figure 17
With RSET = 5.1 kΩ
With RSET = 5.1 kΩ
See Figure 17
TA = 25°C
0.5 V ≤ VCP ≤ VP − 0.5 V
0.5 V ≤ VCP ≤ VP − 0.5 V
VCP = VP/2
The SPI interface is 1.8 V and 3 V logic compatible
Open-drain output chosen, 1 kΩ pull-up resistor
to 1.8 V
CMOS output chosen
TA = 25°C
TA = 25°C
TA = 25°C
Rev. B | Page 3 of 16
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