PDF LMS6002D Data sheet ( Hoja de datos )

Número de pieza	LMS6002D
Descripción	Multi-band Multi-standard Transceiver
Fabricantes	Lime Microsystems
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LMS6002D Multi-band Multi-standard Transceiver with Integrated Dual DACs and ADCs SUMMARY FEATURES  Single chip transceiver covering 0.3-3.8GHz frequency range  Digital interface to baseband with integrated 12 bit D/A and A/D converters  Fully differential baseband signals  Few external components  Programmable modulation bandwidth: 1.5, 1.75, 2.5, 2.75, 3, 3.84, 5, 5.5, 6, 7, 8.75, 10, 12, 14, 20 and 28MHz  Supports both TDD and FDD operation modes  Low voltage operation, 1.8V and 3.3V  120 pin DQFN package  Power down option  Serial port interface APPLICATIONS  Femtocell and Picocell base stations  Repeaters  Broadband wireless communication devices for WCDMA/HSPA, LTE, GSM, CDMA2000, IEEE® 802.16x radios 12 TXD[11:0] TX_IQ_SEL TX_CLK RX_CLK_OUT RX_CLK RX_IQ_SEL RXD[11:0] 12 22 IQ DACs 12 IDAC QDAC 12 /2 TX Power Control TX Gain Control TXLPF TXVGA1 DAC TXMIX LO Leakage TXVGA2 PA1 DAC 0o 90o TXPLL PA2 AUXPA LMS6002D 2 TXOUT1 TXOUT2 2 /2 12 IADC QADC 12 IQ ADCs RXVGA2 RXLPF RXOUTSW 22 RXPLL 0o 90o RXVGA1 RXMIX RX Power Control RX Gain Control LNA1 LNA2 2 2 LNA3 RXLNA 2 RXIN1 RXIN2 RXIN3 SPI Figure 1: Functional block diagram GENERAL DESCRIPTION The LMS6002D is a fully integrated, multi-band, multi-standard RF transceiver for 3GPP (WCDMA/HSPA, LTE), 3GPP2 (CDMA2000) and 4G LTE applications, as well as for GSM pico BTS. It combines the Document version: 1.1.0 Last modified: 03/12/2012 © Copyright Lime Microsystems LNA, PA driver, RX/TX mixers, RX/TX filters, synthesizers, RX gain control, and TX power control with very few external components. The information contained in this document is subject to change without prior notice. Lime Microsystems assumes no responsibility for its use, nor for infringement of patents or other rights of third parties. Lime Microsystems' standard terms and conditions apply at all times. 1 page LMS6002D - Multi-band Multi-standard Transceiver with Integrated Dual DACs and ADCs PVDDSPI33 PVDDSPI33 External PLLCLK CLKBUF External PLLCLK CLKBUF LMS6002D VSS (a) LMS6002D VSS Figure 5: PLL reference clock input buffer, (a) DC coupled (b) AC coupled (b) Parameter Frequency Range Reference Amplitude Reference Frequency Frequency Step Size Phase Noise 10 KHz offset 100 KHz offset 1 MHz offset Phase Noise 10 KHz offset 100 KHz offset 1 MHz offset Phase Noise 10 KHz offset 100 KHz offset 1 MHz offset Reference Spurious Outputs Other Spurious Outputs IQ Phase Error IQ Amplitude Error PLL settling time Condition Min Typ 0.3 At PVDDSPI33=3.3V 0.2 0.8 For continuous LO frequency range 23 At 41MHz reference clock 800MHz -94 -113 -130 1.9GHz -89 -95 -125 2.6GHz -86 -90 -125 800MHz 1.9GHz 2.6GHz To 1ppm, 50kHz loop bandwidth 1 3 9 0.4 20 Table 5: Synthesizer specifications Max 3.8 3.3 41 2.4 Unit GHz Vpp MHz Hz dBc/Hz -50 dBc -50 dBc deg dB μs RF PORTS LMS6002D has two transmitter outputs and three receiver inputs. The transmitter output ports are optimized for a 65Ω differential load, the final stage amplifiers are open drain and require +3.3V voltage supply, see LMS6002D typical application circuit in Figure 19. The receiver inputs are all different. RXIN1 is the low frequency input and can operate in the range 0.3 – 2.8GHz, RXIN2 is the high frequency input and can operate in the range 1.5 – 3.8GHz. Both RXIN1 and RXIN2 require matching circuits for optimum performance. A simple match is shown in Figure 19. RXIN3 is a broadband input covering the range 0.3 – 3.0GHz, it is 200Ω differential and is typically matched with a wideband transformer. TX and RX LOW PASS FILTERS LMS6002D integrates highly selective low pass filters in both TX and RX paths. Filters have a programmable pass band in order to provide more flexibility on the DAC/ADC clock frequency and also to provide excellent adjacent channel rejection in the receive chain. The following LPF pass bands are supported: 14, 10, 7, 6, 5, 4.375, 3.5, 3, 2.75, 2.5, 1.92, 1.5, 1.375, 1.25, 0.875, and 0.75MHz. Filters are also tunable to compensate for process/temperature variation. The TX and RX filters are the same but controlled via SPI link independently. Measured amplitude responses are shown in Figure 6. Assuming 40MHz DAC/ADC clock, 28MHz modulation bandwidth (equivalent to 14MHz baseband IQ bandwidth) and 28MHz channel spacing, performance of the TRX filters is summarised as below. TX low pass filter:  First DAC image attenuation  Second DAC image attenuation >= 55dB >= 70dB LMS6002D 5 © Copyright Lime Microsystems 5 Page Implementing Low Voltage SPI Digital IO buffers and ESD protection diodes in the SPI region are all supplied from a single pin PVDDSPI33. PVDDSPI33 can go below 3.3V to implement low voltage signaling. For example, if PVDDSPI33=2.5V then all data lines in Figure 17, including PLL reference clock input, are set to 2.5V CMOS IOs. There is no dedicated ESD protection diodes supply here so when PVDDSPI33 is less than 3.3V, inputs will not be 3.3V tolerant. Minimum PVDDSPI33 is 1.8V. 1.8 - 3.3 V PVDDSPI IO Buffers and PVDDSPI33 ESD Diodes Supply SEN SDO SDIO CLK SPI RESET TXEN RXEN Chip Control PLLCLK Reference Clock LMS6002D Figure 17: SPI supplies LMS6002D LimeLight™ 11 © Copyright Lime Microsystems 11 Page

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