PDF LMS7002M Data sheet ( Hoja de datos )

Número de pieza	LMS7002M
Descripción	FPRF MIMO Transceiver IC
Fabricantes	Lime Microsystems
Logotipo
Hay una vista previa y un enlace de descarga de LMS7002M (archivo pdf) en la parte inferior de esta página. Total 27 Páginas
No Preview Available ! LMS7002M FPRF MIMO Transceiver IC With Integrated Microcontroller SUMMARY FEATURES  Field Programmable Radio Frequency (FPRF) chip  Dual transceiver ideal for MIMO  User programmable on the fly  Continuous coverage of the 100 kHz - 3.8 GHz RF frequency range  Digital interface to baseband with on chip integrated 12 bit D/A and A/D converters  Programmable RF modulation bandwidth up to 160 MHz using analog interface  Programmable RF modulation bandwidth up to 60 MHz using digital interface  Supports both TDD and full duplex FDD  LimeLight™ digital IQ interface – JEDEC JESD207 TDD and FDD compliant  Transceiver Signal Processor block employs advanced techniques for enhanced performance  Single chip supports 2x2 MIMO. Multiple chips can be used to implement higher order MIMO  On-chip RF calibration circuitry  Fully differential baseband signals, analog IQ  Few external components  Low voltage operation, 1.25, 1.4 and 1.8V. Integrated LDOs to run on a single 1.8V supply voltage  On chip integrated microcontroller for simplified calibration, tuning and control  Integrated clock PLL for flexible clock generation and distribution  User definable analog and digital filters for customised filtering  RF and base band Received Signal Strength Indicator (RSSI)  261 pin aQFN 11.5x11.5 mm package  Power down option  Serial port interface  Low power consumption, typical 880mW in full 2x2 MIMO mode (550mW in SISO mode) using external LDOs  Multiple bypass modes for greater flexibility APPLICATIONS  Broad band wireless communications  GSM, CDMA2000, TD-SCDMA, WCDMA/HSPA, LTE  IEEE® xxx.xxx radios  WiFi operating in the Whitespace frequencies  Software Defined Radio (SDR)  Cognitive Radio  Unmanned Aerial Vehicle (UAV)  Other Whitespace applications Document version: 2.8.0 RXINL RXLNAL RXLNAH RXINH RXLNAW RXINW RF RSSI RXLNAL RXINL RXLNAH RXINH RXLNAW RXINW RXMIX RXTIA RXLPF RXPGA ADC ADC RX LO Chain RX Synthesizer TX BB LPF TX BB LPF RXOUTI, RXOUTQ RXOUTI, RXOUTQ RXOUTSW RXOUTSW RXMIX RXTIA RXLPF RXPGA ADC ADC TXOUT1 TXOUT2 TXOUT1 TXOUT2 RF RSSI Switch Connects to LNA output in RF Loop Back mode Power Det. Power Det. TXPAD RX BB TXPAD Switch Switch Connects to LNA output in RF Loop Back mode Connects to LNA output in RF Loop Back mode Power Det. Power Det. TXPAD RX BB TXPAD Switch Connects to LNA output in RF Loop Back mode SPI Micro Controller Clock PLL TX BB LPF TXINI, TXINQ TXMIX TXLPF DAC DAC TX LO Chain TX Synthesizer TXMIX TXLPF DAC DAC TX BB LPF TXINI, TXINQ Figure 1: Functional block diagram DLB 1 page LMS7002M – FPRF MIMO Transceiver IC Parameter Output Frequency Range Reference Amplitude Reference Frequency Frequency Resolution 850 MHz Phase Noise 1 kHz offset 5 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset 30 MHz offset Min. 30 0.2 10 Typ. 0.8 -96 -97 -99 -107 -131 -158 Max. 3800 2.5 52 24.8 Unit MHz Vpp MHz Hz Condition/Comment At PVDD>2.5V For continuous LO frequency range Using 52 MHz PLL reference clock dBc/Hz 2.0 GHz Phase Noise 1 kHz offset 5 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset 30 MHz offset -91 -92 -92 -102 -127 -158 dBc/Hz 2.7 GHz Phase Noise 1 kHz offset 5 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset 30 MHz offset -87 -88 -92 -98 -123 -158 dBc/Hz 3.5 GHz Phase Noise 1 kHz offset 5 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset 30 MHz offset Reference Spurious Outputs Other Spurious Outputs 850 MHz IQ Phase Error 2000 MHz IQ Phase Error 3500 MHz IQ Phase Error IQ Amplitude Error PLL settling time -84 -85 -86 -89 -113 -152 dBc/Hz -70 -60 0.8 2 3 +/- 0.1 50 -68 -55 1 +/- 0.2 150 dBc dBc degrees degrees degrees dB μs Table 5: Synthesizer specifications After calibration loop BW=70 kHz RF PORTS LMS7002M has two transmitter outputs and three receiver inputs for each of the dual transceivers. The optimum transmitter output load is 40Ω differential at the output pads. The final stage amplifiers are open drain and require +1.8V voltage supply. The receiver inputs are common-source with different inductive degeneration, optimized for different frequency bands. They need to be externally matched for optimized narrowband performance or broadband utilizing a wideband transformer. lower pass band of 0.7 MHz. Using such mixed mode filtering (digital and analog) provides 60 dB anti alias performance and 40 dB adjacent channel rejection as the worst case scenario. The TX filtering chain pass band is tunable from 2 MHz to 80 MHz. When combined with TX digital filters the chain offers enhanced performance in a similar way as the RX analog/digital filtering chain. As shown in Figure 6, transmitter baseband has three independently controlled low pass filter stages: 1. 4th order ladder filter (TXLPFLAD), 2. 1st order real pole filter (TXLPFS5), 3. 2nd order high band filter (TXLPFH). TX and RX LOW PASS FILTERS LMS7002M integrates selective low pass filters in both the TX and RX paths. Filters have programmable pass band in order to provide more flexibility on the DAC/ADC clock frequency and also to provide adjacent channel rejection in the receive chain. The complete filtering function is a combination of analog filtering and digital TSP filtering. RX analog filters are tunable from 0.7 MHz to 80 MHz. The digital filters provide a Low band filter (TXLPFL) path pass band is tunable from 2 MHz to 20 MHz and is comprised of two filter stages: 4th order low pass ladder filter (TXLPFLAD) and 1st order low pass real pole filter (TXLPFS5). The real pole stage filters the BB noise at the duplex frequency to meet the far- end noise specifications in some FDD systems. High band filter (TXLPFH) pass band is tunable from 20 MHz up to 80 MHz and is comprised of a single 2nd order low pass stage. Only one (TXLPFL or TXLPH) path can be active at the same time. LMS7002M 5 5 Page LMS7002M – FPRF MIMO Transceiver IC Memory Bank 0 Memory Bank 1 Memory Bank 4 Figure 29: General purpose FIR filter coefficients memory organisation General purpose FIR filter 3 hardware is composed of three filters (each equivalent to G.P. FIR 1 or 2) running in parallel in order to increase its processing power hence it can implement the filters with: N  3 * 40  120 . It can be used as a channel select filter or for any other purpose which requires a larger number of filtering taps. Received Signal Strength Indicators A digital received signal strength indicator (RSSI) circuit calculates the level of the received complex signal (I + jQ) as follows: RSSI  I 2  Q2 . The following approximation of the square root is implemented in the chip: a2  b2  maxM  0.125M   0.5N , M , where: M  maxa , b . N  mina , b  The same RSSI block is used within the digital AGC loop. If digital AGC is not required then the RSSI output, after being averaged by the COMB filter, can be provided back to the BB modem via SPI as shown in Figure 30. In this way the BB can control RF and IF gain stages to implement analog AGC in which case the AGC loop is closed via the BB modem. There is also an RF RSSI block implemented in the RF front end connected to the input of the wideband LNA. This block can be used to detect the presence of large interferers so the BB modem can adjust RX gain stages very quickly to counteract such scenarios. The RF RSSI output is routed to I ADCs of RX channel 1 or RX channel 2. When the RSSI output is to be read, the main RX path of that channel should be disabled. Also, RF RSSI analog output can be provided off chip at the test pin and further processed by external circuits. In this case none of the RX paths needs to be disabled. The RSSI detects the input from -70 dBm to -20 dBm, corresponding to the full dynamic range of the ADC. Automatic Gain Control The structure of the digital automatic gain control loop is shown in Figure 30. The AGC loop functions as follows:  “Square root of two” (RSSI) block calculates the RMS of the AGC output.  This signal is averaged by the COMB filter. The averaging window size AVG is programmable via SPI.  An error signal is then calculated as the difference between the desired output signal level and the measured one. The desired amplitude level ADESIRED is programmable via SPI.  After the loop gain stage, the error is integrated to construct the digital VGAs gain control signal. Loop gain K is programmable via SPI.  VGAs gain cannot be negative and should not be zero either, hence max(1,x) module is provided in the feedback path. IIN IOUT Integrator Loop Gain RSSI Out Averaging Filter QIN MAX(1, X) Z-1 K/2N-1 error N - + K ADESIRED COMB AVG I2 + Q2 2 QOUT Figure 30: AGC architecture Figure 31 illustrates two possible applications of the digital AGC. The first example (Figure 31.a) shows the case where the BB modem expects 4-bits instead of full 12-bit ADC output. In this case, ADESIRED loop parameter is set as shown in the figure, the gain of RF and IF stages are set for ADC not to produce full scale but ADESIRED level instead. The middle 4 bits are provided to BB. If the RF input signal level goes higher or lower, AGC will adapt the gain to keep its output at ADESIRED value so bits 7 to 4 will always contain 4 MSBs of the received signal. Since we have 4 bits on top and 4 bits below the middle 4 bits, the loop itself provides +/-24 dB automatic gain control range without using RF and IF gain stages. The second example shown in Figure 31.b is a more general case. The BB modem will receive 10-bits while the loop provides +/- 6 dB gain control range without engaging RF and IF gain blocks. ADESIRED 11 10 ADESIRED 9 8 7 6 To BB 5 4 3 2 1 0 (a) 11 10 9 8 7 6 To BB 5 4 3 2 1 0 (b) Figure 31: Truncation to (a) 4 bits and (b) 10 bits LIMELIGHT™ DIGITAL IQ DATA INTERFACE Description The LMS7002M implements LimeLight™ digital IQ interface to the BB modem. LimeLight™ can be configured to run in one of the following three modes: 1. JESD207 mode 2. TRXIQ double data rate (DDR) mode 3. TRXIQ single data rate (SDR) mode All three modes are capable of supporting both TDD and FDD operation. The data throughput of JESD207 and TRX DDR is high enough to connect to up to 2x2 MIMO BB modems. TRXIQ SDR mode is backward compatible to the LMS6002D digital IQ interface. BBIC MCLK FCLK TXNRX ENABLE DIQ[11:0] MCLK_n RFIC FCLK_n TXNRX_n ENABLE_IQSEL_n DIQ[11:0]_n Note: n = 1 for LimeLight Port 1, n = 2 for LimeLight Port 2. Figure 32: LimeLight™ port, JESD mode LMS7002M 11 11 Page

Páginas	Total 27 Páginas
PDF Descargar	[ Datasheet LMS7002M.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
LMS7002M	FPRF MIMO Transceiver IC	Lime Microsystems

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar