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PDF TC518512PI-80 Data sheet ( Hoja de datos )
| Número de pieza | TC518512PI-80 | |
| Descripción | SILICON GATE CMOS PSEUDO STATIC RAM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TOSHIBA
SILICON GATE CMOS
524,288 WORD x 8 BIT CMOS PSEUDO STATIC RAM
11:518512PI/F1~/10
Description
The TC518512PI is a 4M bit high speed CMOS pseudo static RAMorganized as 524,288 words by 8 bits. The TC518512PI utilizes
a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacityJ:!!,9h speed and low power storage. The
TC518512PI operates from a single 5V power supply. Refreshing is supported by a refresh (OEIRFSH) input which enables two
types of refreshing - auto refresh and self refresh. The TC518512PI features a static RAM-like interface with a write cycle in which
the input data is written into the memory cell at the rising edge of RIW thus simplifying the microprocessor interface. The
TC518512PI is guaranteed over an operating temperature range of -40 - 85°C.
The TC518512PI is available in a 32-pin, 0.6 inch width plastic DIP and a small outline plastic flat package.
Features
• Organization: 524,288 words x 8 bits
• Single 5V power supply
• Fast access time
TC518512PI Family
crtCEA Access Time
toEA ~ Access Time
tRC Cycle Time
Power Dissipation
Self Refresh Current
-80 -10
80ns
100ns
30ns
40ns
130ns
160ns
330mW 275mW
300~
• Auto refresh is supported by an internal refresh address
counter
• Self refresh is supported by an internal timer
• Wide operating temperature: -40 - 85°C
• Inputs and outputs TTL compatible
• Refresh: 2048 refresh cycles/32ms
• Package
- TC518512PI: DIP32-P-600
- TC518512FI: SOP32-P-525
Pin Names
AO - A18
R/W
OORFSR
cr
1/01 - 1/08
Voo
GND
Address Inputs
ReadIWrite Control Input
Output Enable Input
Refresh Input
Chip Enable Input
Data Inputs/Outputs
Power
Ground
Pin Connection (Top View)
I'll FI
AlS 32 Voo
A ~6 31 A15
A14 30 At7
A12 29 RJW
A7 28 At3
A6 27 A8
AS 26 A9
A4 25 All
A3 24 ~mH
A2 23 AtO
At 22 tt
AO 21 1108
1/01 20 1107
V02 19 V06
V03 18 1105
GND 17 1104
TOSHIBA AMERICA ELECTRONIC COMPONENTS. INC.
0-197
1 page  
Static RAM
TC518512PI/FI-8011 0
Notes:
1) Stress greater than those listed under "Maximum Ratings" may cause permanent damage to the device.
2) All voltages are referenced to GND.
3) IDDO' IDDF3, and IDDF4 depend on the cycle time.
4) IDOO depends on the output loading. Specified values are obtained with the outputs open.
5) An initial pause of 100llS with high CE is required after power-up before proper device operation is achieved.
6) AC measurements assume tT =5ns.
7) Timing reference levels
Input Levels
Input Reference Levels
Output Reference Levels
V1H =2.6V
V1L =0.6V
V1H = 2.4V
V1L =0.8V
VOH = 2.2V
VOL =0.8V
INPUT
2.6v
O.6V
OUTPUT
INPUT REFERENCE
LEVEL
Z.2V
OUTPUT REFERENCE
LEVEL
8) Measured with a load equivalent to 1 TTL load and 1OOpF.
9) tcHZ, toHZ, tWHZ define the time at which the output achieves the open circuit condition and is not referenced to output
voltage levels.
10) For write cycles, the input data is latched at the earlier of R/W or CE rising edge. Therefore, the input data must be valid
during the setup time (tDSW or tDsd and hold time (tDHW or tDHd.
11) All address inputs are latched at the falling edge of CE. Therefore, all the address inputs must be valid during tASC and tAHC'
12) The two refresh operations, auto refresh and self refresh, are defined by the RFSH pulse width under the condition CE = VH
Auto refresh : RFSH pulse width ~ tFAP (max.)
Self refresh : RFSH pulse width ~ tFAS (min.)
The tim~ng parametertFRs must be met for proper device operation under the following conditions:
• after self refresh
• if OEiRFSH = "L" after power-up
TOSHIBA AMERICA ELECTRDNIC CDMPONENTS, INC.
D-201
5 Page | ||
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| PDF Descargar | [ Datasheet TC518512PI-80.PDF ] | |
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