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TC518512PL-80LV PDF даташит

Спецификация TC518512PL-80LV изготовлена ​​​​«Toshiba» и имеет функцию, называемую «SILICON GATE CMOS PSEUDO STATIC RAM».

Детали детали

Номер произв TC518512PL-80LV
Описание SILICON GATE CMOS PSEUDO STATIC RAM
Производители Toshiba
логотип Toshiba логотип 

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TC518512PL-80LV Даташит, Описание, Даташиты
TOSHIBA
TC518512PL/FL/FIL!fRL70LV/80LV/I0LV
SILICON GATE CMOS
524,288 WORD x 8 BIT CMOS PSEUDO STATIC RAM
Description
The TC518512PL is a 4M bit high speed CMOS pseudo static RAM organized as 524,288 words by 8 bits. The TC518512PL
utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high speed ar}QJow power
storage. The TC518512PL-LVoperates from a single 3.0V - 5.5V power supply. Refreshing is supported by a refresh (05'RFSH)
input which enables two types of refreshing - auto refresh and self refresh. The TC518512PL features a static RAM-like interface
with a write cycle in which the input data is written into the memory cell at the rising edge of RIW thus simplifying the microproces-
sor interface.
The TC518512PL is available in a 32-pin, 0.6 inch width plastic DIP, a small outline plastic flat package, and a thin small outline
package (forward type, reverse type).
Features
• Organization: 524,288 words x 8 bits
• Low voltage operation: 3.0V - 5.5V
• Data retention supply voltage: 3.0V - 5.5V
• Fast access time
TC518512PL-LV Family
crtCEA Access Time
toEA OE Access Time
tRC Cycle Time
Power Dissipation
Self Refresh Current 15.5V
Self Refresh Current 1 3.0V
-70
70ns
30ns
115ns
385mW
-80
80ns
30ns
130ns
330mW
2001lA
1001lA
-10
100ns
40ns
160ns
275mW
• Auto refresh is supported by an internal refresh address
counter
• Self refresh is supported by an internal timer
• Inputs and outputs TIL compatible
• Refresh: 2048 refresh cycles/32ms
• Package
- TC518512PL: DIP32-P-600
- TC518512FL: SOP32-P-525
- TC518512FTL: TSOP32-P-400
- TC518512TRL: TSOP32-P-400A
Pin Names
Al8
Al6
A14
Al2
A7
A6
AS
A4
A3
A2
Al
AO
1101
1102
1103
GNO
Voo
A15
Al7
PJW
Al3
A8
A9
All
O'EIRmi
Aa10
1/08
1107
1/06
1/05
1104
Al8
A16
Al4
Al2
A7
AS
AS
A4
A3
A2
At
AO
1/01
1102
1/03
GNO
AO - A18
RIW
OEii=fFSR
cr
Address Inputs
Read/Write Control Input
Output Enable Input
Refresh Input
Chip Enable Input
1/01 - 1/08
Voo
GND
Data Inputs/Outputs
Power
Ground
TOSHIBA AMERICA ELECTRONIC COMPONENTS. INC.
D-185









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TC518512PL-80LV Даташит, Описание, Даташиты
TC518512PlIFlIFTLlTRL-70LV/80LVI1 OLV
Block Diagram
Voo
Static RAM
COLUMN
DECODER
MEMORY
ARRAY
2048 x 256 x8
REFRESH
TIMER
o=
"
o
"
RJWo---~
Operating Mode
~MODE
Read
Write
cr only Refresh
Auto/Self Refresh
Standby
CE
L
L
L
H
H
OEI
RFSH
L
*
H
L
H
R/W AO -A18 1/01 - 8
H V* OUT
L V* IN
H V* HZ
* * HZ
* * HZ
H = High level input (VIH)
L = Low level input (VIJ
* = VIH orVIL
V* = At the falling edge of CE, all address inputs are latched. At all other times, the address inputs are "*".
HZ = High impedance
Maximum Ratings
SYMBOL
ITEM
VIN Input Voltage
VOUT Output Voltage
Voo Power Supply Voltage
TOPR Operating Temperature
TSTRG Storage Temperature
TSOLOER Soldering Temperature· Time
Po Power Dissipation
lOUT Short Circuit Output Current
RATING
-1.0 - 7.0
-1.0 - 7.0
-1.0 -7.0
0-70
-55 - 150
260·10
600
50
UNIT
V
V
V
°C
°C
°C· sec
mW
mA
NOTES
1
0-186
TOSHIBA AMERICA ELECTRONIC COMPONENTS. INC.









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TC518512PL-80LV Даташит, Описание, Даташиты
Static RAM
TC518512PL/FLlFTlITRL-70LV/80LV/10LV
DC Recommended Operating Conditions
SYMBOL
PARAMETER
Voo Power Supply Voltage
VIH Input High Voltage
VIL Input Low Voltage
MIN. TYP. MAX. UNIT NOTES
4.5 5.0
5.5
V
2.4 - Voo + 1.0 V
-1.0 - 0.8 V
2
DC Characteristics (Ta = 0 - 70°C, Voo = 5V±10%)
SYMBOL
PARAMETER
1000
100S1
100S2
100F1
100F2
100F3
100F4
II(L)
10(L)
VOH
VOL
Operating Current (Average)
cr, Address cycling: tRC = tRC min.
70ns version
80ns version
1OOns version
Standby Current
cr = VIH, OE/Rl~~ = VIH
Standby Current
cr = Voo - 0.2V, OEIRFSH = Voo - 0.2V
Self Refresh Current (Average)
cr = VIH, OE/RFSH = VIL
Self Refresh Current (Average)
cr = Voo - 0.2V, OE/RFSH = 0.2V
Auto Refresh Current (Average)
OE/RFSH cycling: tFC = tFC min.
70ns version
80ns version
1OOns version
CE only Refresh Current (Average)
cr, Address cycling: tRC = tRC min.
70ns version
80ns version
1OOns version
Input Leakage Current
OV ~ VIN ~ Voo, All other Inputs not under test = OV
Output Leakage Current
(crOutput Disabled
= VIH or OE/RF~ = VIH or RIW = Vld
OV ~ VOUT ~ Voo
Output High Level
10H = -1.0mA
Output Low Level
10L = 2.1mA
MIN. TYP.
- 50
- 45
- 35
--
--
--
--
--
--
--
--
--
--
--
--
2.4 -
--
MAX.
70
60
50
UNIT NOTES
mA 3,4
1 mA
200 ~
1 mA
200 ~
70
60 mA
50
70
60 mA
50
±10 ~
3
3
±10 ~
-V
0.4 V
Capacitance* (Voo =5V, Ta =25°C, f =1MHz)
SYMBOL
PARAMETER
CI1 Input Capacitance (AO - A18)
(cr,CI2 Input Capacitance
OE/liF~, RIW)
CIO Input/Output Capacitance
MIN.
-
-
-
*This parameter is periodically sampled and is not 100% tested.
MAX.
5
7
7
UNIT
pF
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
0-187










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