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PDF SN7500 Data sheet ( Hoja de datos )

Número de pieza SN7500
Descripción Pulse Width Modulation
Fabricantes KODENSHI 
Logotipo KODENSHI Logotipo



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No Preview Available ! SN7500 Hoja de datos, Descripción, Manual

SN7500x/P
Pulse Width Modulation
Description
The SN7500 is a monolithic integrated circuit which includes all the necessary
building blocks for the design of pulse width modulate(PWM) switching power supplies,
including push-pull, bridge and series configuration. The precision of voltage reference is
improved up to ±1%/±2% through trimming and this provides a better output voltage
regulation. The device can operate at switching frequencies between 1KHz and 300KHz and
output voltage up to 36V.
The SN7500 is specified over an operating temperature range of -40~+85.
Features
Package Type
Internal Regulator Provides a Stable 5V
Reference Supply Trimmed to ±1% or ±2% Accuracy
Uncommitted output transistors capable
of 200mA source or sink
Internal protection from double pulsing of
out-puts with narrow pulse widths or with
supply voltages below specified limits
Easily synchronized to other circuits
Dead time control comparator
Output control selects single-ended or
push-pull operation
Operating temperature range : -40~ +85
Halogen-Free Package is Available
High Level ESD Protection : 400V(MM), 4KV(HBM)
Application
SOP-16
DIP-16
Charger
SMPS
Back Light Inverter
Ordering Information
Device Name
PKG Type
SN7500x
SOP-16
SN7500xP
DIP-16
Rank X : B = Vref 2% / C = Vref 1%
Marking Information : (1) Device Code, (2) Year & Week Code
Nov, 2011 REV. 00
KSD-I7D003-000
Marking
SN7500---(1)
YWW---(2)
SN7500---(1)
YWW---(2)
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SN7500 pdf
SN7500x/P
INFORMATION
The basic oscillator(switching)frequency is controlled by an external resistor (RT) and
capacitor(CT). The relationship between the values of RT,CT and frequency is shown in.
The level of the sawtooth wave form is compared with an error voltage by the pulse width
modulated comparator. The output of the PWM Comparator directs the pulse steering flip
flop and the output control logic.
The error voltage is generated by the error amplifier. The error amplifier boosts the voltage
difference between the output and the 5V internal reference. See Figure7 for error amp
sensing techniques. The second error amp is typically used to implement current limiting.
The output control logic (Pin13) selects either push-pull or single-ended operation of the
output transistors (see Figure6). The dead time control prevents on-state overlap of the
output transistors as can be seen is Figure5. The dead time is approximately 3 to 5% of the
total period if the dead time control(pin4) is grounded. This dead time can be increased by
connecting the dead time control to a voltage up to 5 V. The frequency response of the
error amps can be modified by using external resistors and capacitors. These components
are typically connected between the compensation terminal (pin3) and the inverting input
of the error amps(pin2 or pin15). The switching frequency of two or more SJ7500 circuits
can be synchronized. The timing capacitor, Ct is connected as shown in Figure8. Charging
current is provided by the master circuit. Discharging is through all the circuits slaved to
the master. Rt is required only for the master circuit.
Operating Waveform
Nov, 2011 REV. 00
KSD-I7D003-000
5

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SN7500 arduino
SN7500x/P
The AUK Corp. products are intended for the use as components in general electronic
equipment (Office and communication equipment, measuring equipment, home
appliance, etc.).
Please make sure that you consult with us before you use these AUK Corp. products
in equipments which require high quality and / or reliability, and in equipments which
could have major impact to the welfare of human life(atomic energy control, airplane,
spaceship, transportation, combustion control, all types of safety device, etc.). AUK
Corp. cannot accept liability to any damage which may occur in case these AUK Corp.
products were used in the mentioned equipments without prior consultation with AUK
Corp..
Specifications mentioned in this publication are subject to change without notice.
Nov, 2011 REV. 00
KSD-I7D003-000
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