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PDF ASP0800 Data sheet ( Hoja de datos )
| Número de pieza | ASP0800 | |
| Descripción | Programmable Multi-Phase Synchronous Buck Converter | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Programmable Multi-Phase Synchronous
Buck Converter with PMBus
Preliminary Technical Data
ASP0800
ERY FEATURES
Selectable 1-, 2-, 3-, 4-, 5-, 6, 7 or 8- phase operation at up to
1 MHz per phase
PMBus Interface - enables digital programmability of set
points and readback of monitored values
Logic-level PWM outputs for interface to external high
power drivers
Fast-Enhanced PWM flex mode for excellent load transient
performance
Active current balancing between all output phases
Built-in power-good/crowbar blanking supports on-the-fly
VID code changes
Digitally programmable 0.375 V to 1.6 V output supports
both VR11 and VR11.1 specifications
Programmable Offset up to ±200mV
Programmable short-circuit protection with programmable
latch-off delay
Supports PSI# – Power saving mode during light loads
Over – Clocking Control
APPLICATIONS
CPU Power controllers for Servers, Workstations and high
end Desktops.
Next generation Intel® VRM modules
POL Applications such as Memory
GENERAL DESCRIPTION
The ASP08001 is an integrated power control IC with a PMBus
interface. The ASP0800 is a highly efficient, multiphase,
synchronous buck switching regulator controller, which aids
design of High Efficiency and High Density solutions.
The PMBus interface enables digital programming of key
system parameters to optimize system performance and provide
feedback to the system. The ASP0800 is compatible for use with
coupled inductors,
The ASP0800 is optimized for converting a 12 V main supply
into the core supply voltage required by high performance Intel
processors. It uses an internal 8-bit DAC to read the voltage
identification (VID) code directly from the processor, which is
used to set the output voltage between 0.375 V and 1.6 V.
This device uses a multimode PWM architecture to drive the
logic-level outputs at a programmable switching frequency that
can be optimized for VR size and efficiency. The ASP0800 can
be programmed for 1-, 2-, 3-, 4-, 5-, 6, 7 or 8- phase operation,
allowing for the construction of up to 8 complementary buck
switching stages. The ASP0800 support PSI#, which is a power
state indicator and can be used to reduce number of operating
Rev. Pr H
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
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Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
VCC
39
SHUNT
REGULATOR
VCC3
1
3.3V
REGULATOR
UVLO
SHUTDOWN
GND 7
850mV
EN/VTT 6
–
+
SCL SDA
54
SMBUS
RT RAMPADJ
12 13
OSCILLATOR
CONTROL
CSREF
CONTROL
–
+
+
–
CONTROL
CURRENT
BALANCING
CIRCUIT
48 PSI#
21 ODN
+
–CM P
+
–CM P
+
–CM P
+
–CM P
+
–CM P
+
–CM P
+
–CM P
+
–CM P
22 OD1
SET EN
RESET
RESET
RESET
38 PWM1
37 PWM2
36 PWM3
RESET 1- 8 PHASE
DRIVER LOGIC
RESET
35 PWM4
34 PWM5
RESET
33 PWM6
RESET
32 PWM7
RESET
31 PWM8
PWRGD 2
ALERT 3
DELAY
COMPARATORS
EN
FB
FBRTN
IMON
MUX
DIGITAL
REGISTERS
ADC
CONTROL
IREF 11
COMP 15
ILIMITFS 20
OC1 8
OC2 9
CLOCK
CONTROL
ASP0800
CONTROL
CROWBAR
CONTROL
CURRENT
MEASUREMENT
AND LIMIT
CONTROL
CURRENT
LIMIT
30 SW1
29 SW2
28 SW3
27 SW4
26 SW5
25 SW6
24 SW7
23 SW8
19 CSCOMP
+ 17 CSREF
–
18 CSSUM
10 IMON
–
+
CONTROL
+
+
–
–
16 FB
PRECISION
REFERENCE
VID DAC
BOOT VOLTAGE&
SOFT START CONTROL
14
FBRTN
47 46 45 44 43
42 41
40
VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7
Figure 1. Functional Block Diagram
phases at light loads.
The ASP0800 includes a PMBus interface, which can be used to
program system set points such as voltage offset, load line,
phase balance and output voltage. Key system performance data
such as CPU current, CPU voltage, and power and fault
conditions can also be read back over the PMBus from the
ASP0800.
The ASP0800 OC Feature allows programming different offset
voltages depending on the load current being supplied. 3 OC
Thresholds and 4 OC Offsets value registers are supported.
The ASP0800 has a built in shunt regulator that allows the part
to be powered from the +12V system supply through a series
resistor. The ASP0800 is specified over the extended
commercial temperature range of 0°C to +85°C and is available
in a 48 Lead LFCSP package.
1 Protected by U.S. Patent Number 6,683,441; other patents pending.
One Technology Way, P.O. Box 9106, NorwooPdu, bMliAcat0io2n06O2r-d9e1r0N6u,mUb.Se.rA: .
Tel: 781.329.4700
www.aAnSaPlo0g80.c0o/mS
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
Parameter
During Soft Start2
VID Code Changing
VID Code Static
Crowbar Trip Point
Overvoltage Adjustment Range Low
Overvoltage Adjustment Range High
Crowbar Reset Point
Crowbar Delay Time
VID Code Changing
VID Code Static
PWM OUTPUTS
Output Low Voltage
Output High Voltage
PMBus Interface
Logic High Input Voltage
Logic Input Low Voltage
Hysteresis
SDA Output Low Voltage
Input Current
Input Capacitance
Clock Frequency
SCL Falling Edge to SDA Valid Time
ALERT FAULT OUTPUTS
Output Low Voltage
Output High Leakage Current
ANALOG/DIGITAL CONVERTER
Total Unadjusted Error (TUE)
Differential Non linearity (DNL)
Conversion Time
SUPPLY
VCC2
DC Supply Current
UVLO Turn-On Current
UVLO Threshold Voltage
UVLO Turn-Off Voltage
VCC3 Output Voltage
Symbol
VCROWBAR
tCROWBAR
VOL(PWM)
VOH(PWM)
VIH(SDA, SCL)
VIL(SDA, SCL)
VOL
IIH ; IIL
CSCL, SDA
fSCL
VOL
IOH
VCC
IVCC
VUVLO
VCC3
Conditions
Internal Timer
Relative to DAC output, PWRGD_Hi = 00
PWRGD_Hi Register = 11
PWRGD_Hi Register = 00
Relative to FBRTN
Overvoltage to PWM going low
IPWM(SINK) = −400 µA
IPWM(SOURCE) = 400 µA
ISDA = −6mA
IOUT = -6mA
VOH = 5V
TBD Bits
Averaging Enabled (32 averages)
VSYSTEM = 12 V, RSHUNT = 340 Ω
VSYSTEM = 13.2 V, RSHUNT = 340 Ω
VCC rising
VCC falling
IVCC3 = 1mA
Min
100
200
250
100
4
2.1
−1
4.70
9
3.0
Typ
2
250
200
300
150
300
300
250
400
160
5
500
5
±2
1
80
5
21
6.5
4.1
3.3
ASP0800
Max Unit
ms
µs
ns
400 mV
mV
mV
350 mV
µs
ns
500 mV
V
V
0.8 V
mV
0.4 V
1 µA
pF
400 kHz
1 µs
0.4 V
1 uA
%
LSB
ms
5.45 V
26 mA
11 mA
V
V
3.6 V
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5 Page 
Preliminary Technical Data
ASP0800
THEORY OF OPERATION
The ASP0800 combines a multi-mode, fixed frequency PWM
control with multi-phase logic outputs for use in multi-phase
synchronous buck CPU core supply power converters. The
internal VID DAC is designed to interface with the Intel 8-bit
VR 11 and VR 11.1 compatible CPUs .
In addition, the ASP0800 incorporates a serial interface to allow
the programming of key system performance specifications and
read back CPU data such as voltage, current and power.
Multiphase operation is important for producing the high
currents and low voltages demanded by today’s
microprocessors. Handling the high currents in a single-phase
converter would place high thermal demands on the
components in the system such as the inductors and MOSFETs.
The multimode control of the ASP0800 ensures a stable, high
performance topology for:
x Balancing currents and thermals between phases for
both static and dynamic operation.
x High speed response at the lowest possible switching
frequency and output decoupling
x FEPWM improves load step response.
x Minimizing thermal switching losses by utilizing
lower frequency operation
x High current output due to 8 phase operation
x Tight load line regulation and accuracy
x Reduced output ripple due to multiphase cancellation
x PC board layout noise immunity
x Ease of use and design due to independent component
selection
x Flexibility in operation for tailoring design to low cost
or high performance
START-UP SEQUENCE
The ASP0800 follows the VR11 start-up sequence shown in
Figure 7. After both the EN and UVLO conditions are met, a
programmable internal timer goes through one cycle TD1. This
delay cycle is programmed using Delay Command, default
delay = 2ms). The first eight clock cycles of TD2 are blanked
from the PWM outputs and used for phase detection as
explained in the following section. Then the programmable
internal soft-start ramp is enabled (TD2) and the output comes
up to the boot voltage of 1.1V. The boot hold time is also set by
the Delay Command. This second delay cycle is called TD3.
During TD3 the processor VID pins settle to the required VID
code. When TD3 is over, the ASP0800 reads the VID inputs
and soft starts either up or down to the final VID voltage
(TD4). After TD4 has been completed and the PWRGD
masking time (equal to VID on the fly masking) is finished, a
third cycle of the internal timer sets the PWRGD blanking
(TD5).
The internal delay and soft start times are programmable using
the serial interface and the Delay Command and Soft Start
Command.
5V
SUPPLY
UVLO
THRESHOLD
VTT I/O
(ADP3298 EN)
VCC_CORE
VR READY
(ADP3298 PWRGD)
0.85V
TD1
TD3
VBOOT
(1.1V)
TD2
VVID
TD4
50µs
TD5
CPU
VID INPUTS
VID INVALID
VID VALID
Figure 7. System Start-Up Sequence for VR11
PHASE DETECTION SEQUENCE
During startup, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the ASP0800 operates as
a 8-phase PWM controller.
To operate as a 7-phase controller connect PWM8 to VCC.
To operate as a 6-phase controller connect PWM7 and PWM8
to VCC.
To operate as a 5-phase controller connect PWM6, PWM7 and
PWM8 to VCC.
To operate as a 4-phaase controller connect PWM5, PWM6,
PWM7 and PWM8 to VCC.
To operate as a 3-phase controller connect PWM4, PWM5,
PWM6, PWM7 and PWM8 to VCC.
To operate as a 2-phase controller connect PWM3, PWM4,
PWM5, PWM6, PWM7 and PWM8 to VCC.
To operate as a 1-phase controller connect PWM2, PWM3,
PWM4, PWM5, PWM6, PWM7 and PWM8 to VCC.
Prior to soft start, while EN is low, the PWM8, PWM7, PWM6,
PWM5, PWM4, PWM3 and PWM2 pins sink approximately
100 µA each. An internal comparator checks each pin’s voltage
vs. a threshold of 3 V. If the pin is tied to VCC, it is above the
threshold. Otherwise, an internal current sink pulls the pin to
GND, which is below the threshold. PWM1 is low during the
phase detection interval that occurs during the first eight clock
cycles of TD2. After this time, if the remaining PWM outputs
are not pulled to VCC, the 100 µA current sink is removed, and
they function as normal PWM outputs. If they are pulled to
Rev. P1 |RPeavg.eP1r 1H|oPf a3g6e| 1w1wowf .3o8nsemi.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ASP0800.PDF ] | |
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