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PDF FPF1038 Data sheet ( Hoja de datos )

Número de pieza FPF1038
Descripción Slew-Rate-Controlled Load Switch
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FPF1038 Hoja de datos, Descripción, Manual

November 2013
FPF1038
Low On-Resistance, Slew-Rate-Controlled Load Switch
Features
1.2 V to 5.5 V Input Voltage Operating Range
Typical RON:
20 mΩ at VIN=5.5 V
21 mΩ at VIN=4.5 V
37 mΩ at VIN=1.8 V
75 mΩ at VIN=1.2 V
Slew Rate / Inrush Control with tR: 2.7 ms (Typical)
3.5 A Maximum Continuous Current Capability
Low <1 µA Shutdown Current
ESD Protected: Above 8 kV HBM, 1.5 kV CDM
GPIO / CMOS-Compatible Enable Circuitry
Applications
HDD, Storage, and Solid-State Memory Devices
Portable Media Devices, UMPC, Tablets, MIDs
Wireless LAN Cards and Modules
SLR Digital Cameras
Portable Medical Devices
GPS and Navigation Equipment
Industrial Handheld and Enterprise Equipment
Description
The FPF1038 advanced load-management switch target
applications requiring a highly integrated solution for
disconnecting loads powered from DC power rail (<6 V)
with stringent shutdown current targets and high load
capacitances (up to 200 µF). The FPF1038 consists of
slew-rate controlled low-impedance MOSFET switch
(21 typical) and other integrated analog features.
The slew-rate controlled turn-on characteristic prevents
inrush current and the resulting excessive voltage droop
on power rails.
These devices have exceptionally low shutdown current
drain (<1 µA maximum) that facilitates compliance in
low standby power applications. The input voltage range
operates from 1.2 V to 5.5 V DC to support a wide range
of applications in consumer, optical, medical, storage,
portable, and industrial device power management.
Switch control is managed by a logic input (active HIGH)
capable of interfacing directly with low-voltage control
signal / GPIO with no external pull-up required. The
device is packaged in advanced fully “green” 1mm
x1.5 mm Wafer-Level Chip-Scale Packaging (WLCSP);
providing excellent thermal conductivity, small footprint,
and low electrical resistance for wider application usage.
Ordering Information
Part Number
Top
Mark
Switch RON
(Typical)
at 4.5 VIN
FPF1038UCX QE
21
Input Output ON Pin
Buffer Discharge Activity
tR
Package
CMOS
NA
Active
HIGH
2.7 ms
6-Bump, WLCSP, 1.0 mm
x 1.5 mm, 0.5 mm Pitch
© 2010 Fairchild Semiconductor Corporation
FPF1038 • Rev. 1.0.6
www.fairchildsemi.com

1 page




FPF1038 pdf
Electrical Characteristics
Unless otherwise noted, VIN=1.2 to 5.5 V and TA=-40 to +85°C; typical values are at VIN=4.5 V and TA=25°C.
Symbol
Parameters
Conditions
Min. Typ. Max. Units
Basic Operation
VIN Input Voltage
1.2
IQ(OFF) Off Supply Current
VON=GND, VOUT=Open
ISD Shutdown Current
VON=GND, VOUT=GND
IQ Quiescent Current
IOUT=0 mA
VIN=5.5 V, IOUT=1 A(3)
RON On Resistance
VIN=4.5 V, IOUT=1 A, TA=25°C
VIN=3.3 V, IOUT=500 mA(3)
VIN=2.5 V, IOUT=500 mA(3)
VIN=1.8 V, IOUT=250 mA(3)
VIN=1.2 V, IOUT=250 mA, TA=25°C
VIH On Input Logic HIGH Voltage
1.0
VIL On Input Logic LOW Voltage
ION On Input Leakage
Dynamic Characteristics
tDON
tR
tON
tDOFF
tF
tOFF
Turn-On Delay(4)
VOUT Rise Time(4)
Turn-On Time(6)
Turn-Off Delay(4)
VOUT Fall Time(4)
Turn-Off(7)
VIN=4.5 V, RL=5 Ω, CL=100 µF,
TA=25°C
VIN=4.5 V, RL=150 Ω, CL=100 µF,
TA=25°C, No Load Discharge
Notes:
3. This parameter is guaranteed by design and characterization; not production tested.
4. tDON/tDOFF/tR/tF are defined in Figure 27.
5. Output discharge enabled during off-state.
6. tON=tR + tDON
7. tOFF=tF + tDOFF
0.2
5.5
20
21
24
28
37
75
1.7
2.7
4.4
2.0
30.0
32.0
5.5
1.0
1.0
8.0
24
25
29
35
45
100
0.4
1.0
V
μA
μA
μA
V
V
μA
ms
ms
ms
ms
ms
ms
© 2010 Fairchild Semiconductor Corporation
FPF1038 • Rev. 1.0.6
5
www.fairchildsemi.com

5 Page





FPF1038 arduino
Physical Dimensions
0.03 C
2X
E AF
B
BALL A1
INDEX AREA
D
TOP VIEW
0.03 C
2X
0.05 C
0.06 C
0.625
0.539
E
(Ø0.350)
SOLDER MASK
OPENING
A1
(Ø0.250)
Cu Pad
(1.00)
(0.50)
RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
0.332±0.018
0.250±0.025
C SEATING PLANE D
SIDE VIEWS
0.50
0.005 C A B
Ø0.315 +/- .025
6X
1.00
0.50
C
B (Y) ±0.018
A
12
F
(X) ±0.018
BOTTOM VIEW
NOTES:
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCE
PER ASMEY14.5M, 1994.
D. DATUM C IS DEFINED BY THE SPHERICAL
CROWNS OF THE BALLS.
E. PACKAGE NOMINAL HEIGHT IS 582 MICRONS
±43 MICRONS (539-625 MICRONS).
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
G. DRAWING FILNAME: MKT-UC006AFrev2.
Figure 30. 6 Ball, 1.0 x 1.5 mm Wafer-Level Chip-Scale Packaging (WLCSP)
Nominal Values
Bump
Pitch
Overall Package
Height
Silicon
Thickness
Solder Bump
Height
Solder Bump
Diameter
0.5 mm
0.582 mm
0.332 mm
0.250 mm
0.315 mm
Product-Specific Dimensions
Product
D
FPF1038UCX
1.5 mm ±0.03
E
1.0 mm ±0.03
X
0.240 mm
Y
0.240 mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2010 Fairchild Semiconductor Corporation
FPF1038 • Rev. 1.0.6
11
www.fairchildsemi.com

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