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PDF AD9641 Data sheet ( Hoja de datos )
| Número de pieza | AD9641 | |
| Descripción | 1.8V Serial Output Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
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Data Sheet
14-Bit, 80 MSPS/155 MSPS, 1.8 V
Serial Output Analog-to-Digital Converter (ADC)
AD9641
FEATURES
JESD204A coded serial digital outputs
SNR = 73.7 dBFS at 70 MHz/80 MSPS
SNR = 72.8 dBFS at 70 MHz and 155 MSPS
SFDR = 94 dBc at 70 MHz and 80 MSPS
SFDR = 90 dBc at 70 MHz and 155 MSPS
Low power: 238 mW at 80 MSPS, 313 mW at 155 MSPS
1.8 V supply operation
Integer 1-to-8 input clock divider
IF sampling frequencies to 250 MHz
−148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS
−148.1 dBFS/Hz input noise at 180 MHz and 155 MSPS
Programmable internal ADC voltage reference
Flexible analog input range: 1.4 V p-p to 2.1 V p-p
ADC clock duty cycle stabilizer (DCS)
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G and 4G)
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
GENERAL DESCRIPTION
The AD9641 is a 14-bit, 80 MSPS/155 MSPS analog-to-digital
converter (ADC) with a high speed serial output interface. The
AD9641 is designed to support communications applications
where high performance, combined with low cost, small size, and
versatility, is desired. The JESD204A high speed serial interface
reduces board routing requirements and lowers pin count
requirements for the receiving device.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth, differential sample-and-hold,
analog input amplifiers that support a variety of user-selectable
input ranges. An integrated voltage reference eases the design
considerations. A duty cycle stabilizer (DCS) is provided to
compensate for variations in the ADC clock duty cycle,
allowing the converter to maintain excellent performance.
FUNCTIONAL BLOCK DIAGRAM
AVDD
SDIO SCLK CSB
DRVDD
AD9641
SPI
VIN+
VIN–
VCM
PROGRAMMING DATA
ADC
REFERENCE
MULTICHIP
SYNC
DATA RATE
MULTIPLIER
DUTY CYCLE
STABILIZER
DIVIDE-BY-1
TO
DIVIDE-BY-8
DOUT+
DOUT–
DSYNC+
DSYNC–
CLK+
CLK–
AGND
SYNC
PDWN DRGND
Figure 1.
The ADC output data is routed directly to the JESD204A serial
output port. This output is at CML voltage levels. A CMOS or
LVDS synchronization input (DSYNC) is provided.
The flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-wire
SPI-compatible serial interface.
The AD9641 is available in a 32-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C.
This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. An on-chip PLL allows users to provide a single ADC
sampling clock. The PLL multiplies the ADC sampling clock
to produce the corresponding JESD204A data rate clock.
2. The configurable JESD204A output block coded data rate
supports up to 1.6 Gbps.
3. A proprietary differential input maintains excellent SNR
performance for input frequencies of up to 250 MHz.
4. Operation is from a single 1.8 V power supply.
5. The standard serial port interface (SPI) supports various
product features and functions, such as data formatting
(offset binary, twos complement, or Gray coding), control-
ling the clock DCS, power-down, test modes, voltage
reference mode, and serial output configuration.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
1 page  
AD9641
Data Sheet
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, DCS enabled,
unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 10 MHz
fIN = 70 MHz
fIN = 180 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 10 MHz
fIN = 70 MHz
fIN = 180 MHz
fIN = 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 70 MHz
fIN = 180 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 10 MHz
fIN = 70 MHz
fIN = 180 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 10 MHz
fIN = 70 MHz
fIN = 180 MHz
fIN = 220 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 10 MHz
fIN = 70 MHz
fIN = 180 MHz
fIN = 220 MHz
TWO-TONE SFDR
fIN = 30 MHz (−7 dBFS ), 33 MHz (−7 dBFS )
fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS )
ANALOG INPUT BANDWIDTH2
Temperature
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
AD9641-80
AD9641-155
Min Typ Max Min Typ Max Unit
73.8
73.7
72.6
71.8
71.3
72.0
71.7
71.3
69.8
71.2
dBFS
dBFS
dBFS
dBFS
dBFS
73.7
73.6
72.5
71.4
71.2
71.0
70.6
70.2
68.7
70.1
dBFS
dBFS
dBFS
dBFS
dBFS
12.0 11.5 Bits
11.9 11.4 Bits
11.8 11.4 Bits
11.5 11.4 Bits
−94
−94
−91
−80
−90
−91
−91
−90
−80
−89
dBc
dBc
dBc
dBc
dBc
94
94
91
80
90
91
91
90
80
89
dBc
dBc
dBc
dBc
dBc
−98
−98
−96
−90
−90
−96
−98
−94
−87
−90
dBc
dBc
dBc
dBc
dBc
93 89 dBc
89 89 dBc
780 780 MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 The analog input bandwidth parameter specifies the −3 dB input BW of the AD9641 input. The usable full-scale BW of the part with good performance is 250 MHz.
Rev. B | Page 4 of 36
5 Page 
AD9641
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum sample rate per speed grade, DCS enabled, 1.75 V p-p differential input, VIN =
−1.0 dBFS, and 32k sample, TA = 25°C, unless otherwise noted.
00
80MSPS
80MSPS
10.1MHz @ –1dBFS
140.3MHz @ –1dBFS
–20
SNR = 73.0dB (74.0dBFS)
–20 SNR = 72.2dB (73.2dBFS)
SFDR = 95dBc
SFDR = 94.0dBc
–40 –40
–60 –60
–80
–100
THIRD HARMONIC
–80
–100
–120
–120
–140
0
10 20 30
FREQUENCY (MHz)
40
Figure 5. AD9641-80 Single-Tone FFT with fIN = 10.1 MHz
–140
0
10 20 30
FREQUENCY (MHz)
40
Figure 8. AD9641-80 Single-Tone FFT with fIN = 140.1 MHz
0
80MSPS
30.1MHz @ –1dBFS
–20 SNR = 72.7dB (73.7dBFS)
SFDR = 94dBc
–40
0
80MSPS
180.1MHz @ –1dBFS
–20 SNR = 71.6dB (72.6dBFS)
SFDR = 93dBc
–40
–60
–80
–100
SECOND HARMONIC
THIRD HARMONIC
–60
–80
–100
SECOND HARMONIC
–120
–120
–140
0
10 20 30
FREQUENCY (MHz)
40
Figure 6. AD9641-80 Single-Tone FFT with fIN = 30.1 MHz
–140
0
10 20 30
FREQUENCY (MHz)
40
Figure 9. AD9641-80 Single-Tone FFT with fIN = 180.1 MHz
00
80MSPS
80MSPS
–20
70.1MHz @ –1dBFS
SNR = 72.5dB (73.5dBFS)
220.1MHz @ –1dBFS
–20 SNR = 71.1dB (72.1dBFS)
SFDR = 94.0dBc
SFDR = 92dBc
–40 –40
–60
–80
–100
–120
SECOND HARMONIC
THIRD HARMONIC
–60
–80
–100
–120
THIRD HARMONIC
SECOND HARMONIC
–140
0
10 20 30
FREQUENCY (MHz)
40
Figure 7. AD9641-80 Single-Tone FFT with fIN = 70.1 MHz
–140
0
10 20 30
FREQUENCY (MHz)
40
Figure 10. AD9641-80 Single-Tone FFT with fIN = 220.1 MHz
Rev. B | Page 10 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9641.PDF ] | |
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