PDF AD9508 Data sheet ( Hoja de datos )

Número de pieza	AD9508
Descripción	1.65 GHz Clock Fanout Buffer
Fabricantes	Analog Devices
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Data Sheet 1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust AD9508 FEATURES 1.65 GHz differential clock inputs/outputs 10-bit programmable dividers, 1 to 1024, all integers Up to 4 differential outputs or 8 CMOS outputs Pin strapping capability for hardwired programming at power-up <115 fs rms broadband random jitter (see Figure 25) Additive output jitter: 41 fs rms typical (12 kHz to 20 MHz) Excellent output-to-output isolation Automatic synchronization of all outputs Single 2.5 V/3.3 V power supply Internal LDO (low drop-out) voltage regulator for enhanced power supply immunity Phase offset select for output-to-output coarse delay adjust 3 programmable output logic levels, LVDS, HSTL, and CMOS Serial control port (SPI/I2C) or pin-programmable mode Space-saving 24-lead LFCSP APPLICATIONS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure GENERAL DESCRIPTION The AD9508 provides clock fanout capability in a design that emphasizes low jitter to maximize system performance. This device benefits applications like clocking data converters with demanding phase noise and low jitter requirements. There are four independent differential clock outputs, each with various types of logic levels available. Available logic types include LVDS (1.65 GHz), HSTL (1.65 GHz), and 1.8 V CMOS (250 MHz). In 1.8 V CMOS output mode, the differential output becomes two CMOS single-ended signals. The CMOS outputs are 1.8 V logic levels, regardless of the operating supply voltage. FUNCTIONAL BLOCK DIAGRAM AD9508 CLK CLK SCLK/SCL/S0 SDIO/SDA/S1 SDO/S3 CS/S2 CONTROL INTERFACE SPI/I2C/PINS DIV/Φ DIV/Φ DIV/Φ DIV/Φ OUT0 OUT0 OUT1 OUT1 OUT2 OUT2 OUT3 OUT3 PIN CONTROL RESET Figure 1. SYNC Each output has a programmable divider that can be bypassed or be set to divide by any integer up to 1024. In addition, the AD9508 supports a coarse output phase adjustment between the outputs. The device can also be pin programmed for various fixed configurations at power-up without the need for SPI or I2C programming. The AD9508 is available in a 24-lead LFCSP and operates from a either a single 2.5 V or 3.3 V supply. The temperature range is −40°C to +85°C. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page AD9508 Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS Typical values are given for VS = 3.3 V and 2.5 V and TA = 25°C; minimum and maximum values are given over the full VDD = 3.3 V + 5% down to 2.5 V − 5% and TA = −40°C to +85°C variation; and input slew rate > 1 V/ns, unless otherwise noted. POWER SUPPLY CURRENT AND TEMPERATURE CONDITIONS Table 1. Parameter SUPPLY VOLTAGE CURRENT CONSUMPTION LVDS Configuration HSTL Configuration CMOS Configuration Full Power-Down TEMPERATURE Ambient Temperature Range, TA Junction Temperature, TJ Min Typ 2.375 2.5 Max 3.465 165 122 194 131 92 141 122 85 6 −40 +25 182 134 213 144 101 185 134 94 10 +85 115 Unit Test Conditions/Comments V Use supply voltage setting (2.5 V or 3.3 V) and appropriate current consumption configuration (see Current Consumption parameters in Table 1) to calculate total power dissipation mA Input clock: 1500 MHz in differential mode, all LVDS output drivers at 1500 MHz mA Input clock: 800 MHz in differential mode, all LVDS output drivers at 200 MHz mA Input clock: 1500 MHz in differential mode, all HSTL output drivers at 1500 MHz mA Input clock: 491.52 MHz in differential mode, all output drivers at 491.52 MHz mA Input clock: 122.88 MHz in differential mode, all output drivers at 122.88 MHz mA Input clock: 1500 MHz in differential mode, all CMOS output drivers at 250 MHz, 10 pF load mA Input clock: 800 MHz in differential mode, all CMOS outputs drivers at 200 MHz, 10 pF load mA Input clock: 100 MHz in differential mode, all CMOS outputs drivers at 100 MHz, 10 pF load mA °C °C Junction temperatures above 115°C can degrade performance but no damage should occur, unless the absolute temperature is exceeded Rev. F \| Page 4 of 40 5 Page AD9508 CLOCK OUTPUT ADDITIVE TIME JITTER Table 9. Parameter LVDS OUTPUT ADDITIVE TIME JITTER CLK = 622.08 MHz, Outputs = 622.08 MHz CLK = 622.08 MHz, Outputs = 155.52 MHz CLK = 125 MHz, Outputs = 125 MHz CLK = 400 MHz, Outputs = 50 MHz HSTL OUTPUT ADDITIVE TIME JITTER CLK = 622.08 MHz, Outputs = 622.08 MHz CLK = 622.08 MHz, Outputs = 155.52 MHz CMOS OUTPUT ADDITIVE TIME JITTER CLK = 100 MHz, Outputs = 100 MHz Data Sheet Min Typ 41 70 69 93 144 142 105 209 206 184 41 56 72 70 76 87 158 156 91 Max Unit Test Conditions/Comments fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms BW = 12 kHz to 20 MHz BW = 20 kHz to 80 MHz BW = 50 kHz to 80 MHz BW = 12 kHz to 20 MHz BW = 20 kHz to 80 MHz BW = 50 kHz to 80 MHz BW = 12 kHz to 20 MHz BW = 20 kHz to 80 MHz BW = 50 kHz to 80 MHz BW = 12 kHz to 20 MHz fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 20 kHz to 80 MHz BW = 50 kHz to 80 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 20 kHz to 80 MHz BW = 50 kHz to 80 MHz fs rms BW = 12 kHz to 20 MHz Rev. F \| Page 10 of 40 11 Page

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