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PDF ADM1026 Data sheet ( Hoja de datos )
| Número de pieza | ADM1026 | |
| Descripción | Complete Thermal System Management Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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ADM1026
Complete Thermal System
Management Controller
The ADM1026 is a complete system hardware monitor for
microprocessor-based systems, providing measurement and limit
comparison of various system parameters. The ADM1026 has up to 19
analog measurement channels. Fifteen analog voltage inputs are
provided, five of which are dedicated to monitoring +3.3 V, +5.0 V,
and 12 V power supplies, and the processor core voltage. The
ADM1026 can monitor two other power supply voltages by
measuring its own VCC and the main system supply. One input (two
pins) is dedicated to a remote temperature-sensing diode. Two
additional pins can be configured as general-purpose analog inputs to
measure 0 V to 2.5 V, or as a second temperature sensing input. The
eight remaining inputs are general-purpose analog inputs with a range
of 0 V to 2.5 V or 0 V to 3.0 V. The ADM1026 also has an on-chip
temperature sensor.
The ADM1026 has eight pins that can be configured for fan speed
measurement or as general-purpose logic I/O pins. Another eight pins are
dedicated to general-purpose logic I/O. An additional pin can be
configured as a general-purpose I/O or as the bidirectional THERM pin.
Measured values can be read out via a 2-wire serial system
management bus, and values for limit comparisons can be
programmed over the same serial bus. The high speed, successive
approximation ADC allows frequent sampling of all analog channels
to ensure a fast interrupt response to any out-of-limit measurement.
Features
Up to 19 Analog Measurement Channels
(Including Internal Measurements)
Up to 8 Fan Speed Measurement Channels
Up to 17 General-Purpose Logic I/O Pins
Remote Temperature Measurement with Remote Diode (Two Channels)
On-Chip Temperature Sensor
Analog and PWM Fan Speed Control Outputs
2-Wire Serial System Management Bus (SMBus)
8 kB On-Chip EEPROM
Full SMBus 1.1 Support Includes Packet Error Checking (PEC)
Chassis Intrusion Detection
Interrupt Output (SMBAlert)
Reset Input, Reset Outputs
Thermal Interrupt (THERM) Output
Limit Comparison of All Monitored Values
This is a Pb-Free Device*
http://onsemi.com
LQFP−48
CASE 932
MARKING DIAGRAM
ADM1026
JSTZ
#YYWW
1
ADM1026JSTZ = Special Device Code
# = Pb-Free Package
YYWW
= Date Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 54 of this data sheet.
Applications
Network Servers and Personal Computers
Telecommunications Equipment
Test Equipment and Measuring Instruments
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2012
April, 2012 − Rev. 4
1
Publication Order Number:
ADM1026/D
1 page  
ADM1026
Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1, 2, and 3))
Parameter
Test Conditions/Comments
Min Typ Max Unit
POWER SUPPLY
Supply Voltage, 3.3 V STBY
3.0 3.3 5.5
V
Supply Current, ICC
TEMPERATURE-TO-DIGITAL CONVERTER
Interface Inactive, ADC Active
− 2.5 4.0 mA
Internal Sensor Accuracy
Resolution
External Diode Sensor Accuracy
Resolution
Remote Sensor Source Current
0C < TD < 100C
High Level
Low Level
− − 3.0 C
− 1.0 −
C
− − 3.0 C
− 1.0 −
C
− 90 −
− 5.5 −
mA
ANALOG-TO-DIGITAL CONVERTER
(Including MUX and ATTENUATORS)
Total Unadjusted Error (TUE) (Note 4)
Differential Non-linearity (DNL)
Power Supply Sensitivity
Conversion Time
(Analog Input or Internal Temperature) (Note 5)
− − 2.0 %
− − 1.0 LSB
− 0.1
%/V
−
11.38 12.06
ms
Conversion Time (External Temperature) (Note 5)
−
34.13 36.18
ms
Input Resistance (+5.0 VIN, VCCP, AIN0 − AIN5)
Input Resistance of +12 VIN pin
Input Resistance of −12 VIN pin
Input Resistance (AIN6 − AIN9)
Input Resistance of VBAT pin (Note 4)
VBAT Current Drain (when measured)
VBAT Current Drain (when not measured)
ANALOG OUTPUT (DAC)
CR2032 Battery Life >10 Years
80 100 120 kW
70 100 115 kW
8.0 10 12 kW
5.0 −
− MW
80 100 120 kW
− 80 100 nA
− 6.0 −
nA
Output Voltage Range
0 –2.5 −
V
Total Unadjusted Error (TUE)
Zero Error
IL = 2 mA
No Load
− − 5.0 %
− 1.0 − LSB
Differential Non-linearity (DNL)
Integral Non-linearity
Output Source Current
Monotonic by Design
− − 1.0 LSB
− 0.5 − LSB
− 2.0 − mA
Output Sink Current
− 1.0 − mA
REFERENCE OUTPUT
Output Voltage
Bit 2 of Register 07h = 0
Bit 2 of Register 07h = 1
1.8 1.82 1.84
2.47 2.50 2.53
V
Load Regulation (ISINK = 2 mA)
Load Regulation (ISOURCE = 2 mA)
Short Circuit Current
Output Current Source
VCC = 3.3 V
− 0.15 −
− 0.15 −
− 25 −
− 2.0 −
%
%
mA
mA
Output Current Sink
− 2.0 − mA
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5 Page 
ADM1026
ADM1026 is powered down, unlike the data in the volatile
registers. Although referred to as read-only memory, the
EEPROM can be written to (as well as read from) via the
serial bus in exactly the same way as the other registers. The
main differences between the EEPROM and other registers
are:
An EEPROM location must be blank before it can be
written to. If it contains data, it must first be erased.
Writing to EEPROM is slower than writing to RAM.
Writing to the EEPROM should be restricted because
its typical cycle life is 100,000 write operations, due to
the usual EEPROM wear-out mechanisms.
The EEPROM in the ADM1026 has been qualified for
two key EEPROM memory characteristics: memory cycling
endurance and memory data retention.
Endurance qualifies the ability of the EEPROM to be
cycled through many program, read, and erase cycles. In real
terms, a single endurance cycle is composed of four
independent, sequential events, as follows:
1. Initial page erase sequence
2. Read/verify sequence
3. Program sequence
4. Second read/verify sequence
In reliability qualification, every byte is cycled from 00h
to FFh until a first fail is recorded, signifying the endurance
limit of the EEPROM memory.
Retention quantifies the ability of the memory to retain its
programmed data over time. The EEPROM in the ADM1026
has been qualified in accordance with the formal JEDEC
Retention Lifetime Specification (A117) at a specific junction
temperature (TJ = 55C) to guarantee a minimum of 10 years
retention time. As part of this qualification procedure, the
EEPROM memory is cycled to its specified endurance limit
described above before data retention is characterized. This
means that the EEPROM memory is guaranteed to retain its
data for its full specified retention lifetime every time the
EEPROM is reprogrammed. Note that retention lifetime
based on an activation energy of 0.6 V derates with TJ, as
shown in Figure 15.
300
250
200
150
100
50
0
40 50 60 70 80 90 100 110 120
JUNCTION TEMPERATURE (5C)
Figure 15. Typical EEPROM Memory Retention
Serial Bus Interface
Control of the ADM1026 is carried out via the serial
system management bus (SMBus). The ADM1026 is
connected to this bus as a slave device, under the control of
a master device.
The ADM1026 has a 7-bit serial bus slave address. When
the device is powered on, it does so with a default serial bus
address. The 5 MSBs of the address are set to 01011, and the
2 LSBs are determined by the logical states of Pin 15
ADD/NTESTOUT. This pin is a three-state input that can be
grounded, connected to VCC, or left open-circuit to give
three different addresses.
Table 6. ADDRESS PIN TRUTH TABLE
ADD Pin
A1
A0
GND
No Connect
VCC
0
1
0
0
0
1
If ADD is left open-circuit, the default address is 0101110
(5Ch). ADD is sampled only at powerup on the first valid
SMBus transaction, so any changes made while the power
is on (and the address is locked) have no effect.
The facility to make hardwired changes to device
addresses allows the user to avoid conflicts with other
devices sharing the same serial bus, for example if more than
one ADM1026 is used in a system.
General SMBus Timing
Figure 16 and Figure 17 show timing diagrams for general
read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types
of read and write operations, which are discussed later in this
section. The general SMBus protocol* operates as follows:
1. The master initiates data transfer by establishing a
start condition, defined as a high-to-low transition
on the serial data line (SDA) while the serial clock
line SCL remains high. This indicates that a data
stream follows. All slave peripherals connected to
the serial bus respond to the start condition and
shift in the next 8 bits, consisting of a 7-bit slave
address (MSB first) and an R/W bit, which
determine the direction of the data transfer, that is,
whether data is written to or read from the slave
device (0 = write, 1 = read).
The peripheral whose address corresponds to the
trans-mitted address responds by pulling the data
line low during the low period before the ninth
clock pulse, known as the acknowledge bit, and
holding it low during the high period of this clock
pulse. All other devices on the bus remain idle
while the selected device waits for data to be read
from or written to it. If the R/W bit is 0, the master
writes to the slave device. If the R/W bit is 1, the
master reads from the slave device.
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| PDF Descargar | [ Datasheet ADM1026.PDF ] | |
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