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PDF AD9433 Data sheet ( Hoja de datos )
| Número de pieza | AD9433 | |
| Descripción | IF Sampling ADC | |
| Fabricantes | Analog Devices | |
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FEATURES
IF sampling up to 350 MHz
SNR: 67.5 dB, fIN up to Nyquist at 105 MSPS
SFDR: 83 dBc, fIN = 70 MHz at 105 MSPS
SFDR: 72 dBc, fIN = 150 MHz at 105 MSPS
2 V p-p analog input range
On-chip clock duty cycle stabilization
On-chip reference and track-and-hold
SFDR optimization circuit
Excellent linearity
DNL: ±0.25 LSB (typical)
INL: ±0.5 LSB (typical)
750 MHz full power analog bandwidth
Power dissipation: 1.35 W (typical) at 125 MSPS
Twos complement or offset binary data format
5.0 V analog supply operation
2.5 V to 3.3 V TTL/CMOS outputs
APPLICATIONS
Cellular infrastructure communication systems
3G single- and multicarrier receivers
IF sampling schemes
Wideband carrier frequency systems
Point-to-point radios
LMDS, wireless broadband
MMDS base station units
Cable reverse path
Communications test equipment
Radar and satellite ground systems
GENERAL INTRODUCTION
The AD9433 is a 12-bit, monolithic sampling analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit and is
designed for ease of use. The product operates up to a 125 MSPS
conversion rate and is optimized for outstanding dynamic per-
formance in wideband and high IF carrier systems.
The ADC requires a 5 V analog power supply and a differential
encode clock for full performance operation. No external refer-
ence or driver components are required for many applications.
The digital outputs are TTL-/CMOS-compatible, and a separate
output power supply pin supports interfacing with 3.3 V or
2.5 V logic.
12-Bit, 105 MSPS/125 MSPS,
IF Sampling ADC
AD9433
FUNCTIONAL BLOCK DIAGRAM
VCC
AD9433
VDD
AIN
AIN
T/H
PIPELINE 12
ADC
OUTPUT 12
STAGING
D11 TO D0
ENCODE
ENCODE
ENCODE
TIMING
REF
DFS
SFDR
MODE
GND
VREFOUT VREFIN
Figure 1.
A user-selectable, on-chip proprietary circuit optimizes
spurious-free dynamic range (SFDR) vs. signal-to-noise and
distortion (SINAD) ratio performance for different input signal
frequencies, providing as much as 83 dBc SFDR performance
over the dc to 70 MHz band.
The encode clock supports either differential or single-ended
input and is PECL-compatible. The output format is user-
selectable for offset binary or twos complement and provides
an overrange (OR) signal.
Fabricated on an advanced BiCMOS process, the AD9433 is
available in a 52-lead thin quad flat package (TQFP_EP) that
is specified over the industrial temperature range of −40°C to
+85°C. The AD9433 is pin-compatible with the AD9432.
PRODUCT HIGHLIGHTS
1. IF Sampling.
The AD9433 maintains outstanding ac performance up to
input frequencies of 350 MHz. Suitable for 3G wideband
cellular IF sampling receivers.
2. Pin-Compatibility with the AD9432.
The AD9433 has the same footprint and pin layout as the
AD9432 12-bit 80 MSPS/105 MSPS ADC.
3. SFDR Performance.
A user-selectable, on-chip circuit optimizes SFDR
performance as much as 83 dBc from dc to 70 MHz.
4. Sampling Rate.
At 125 MSPS, the AD9433 is ideally suited for wireless and
wired broadband applications such as LMDS/MMDS and
cable reverse path.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2001–2009 Analog Devices, Inc. All rights reserved.
1 page  
AD9433
Parameter
DIGITAL OUTPUTS
Logic 1 Voltage
Logic 0 Voltage
Output Coding
Test 105 MSPS
125 MSPS
Temp Level Min
Typ
Max Min
Typ
Max Unit
Full VI
Full VI
VDD − 0.05
0.05
Twos complement or offset binary
VDD − 0.05
0.05
Twos complement or offset binary
V
V
1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and a 2 V p-p differential analog input).
2 SFDR mode disabled (SFDR MODE = GND) for DNL and INL specifications.
3 Power dissipation measured with rated encode and a dc analog input (outputs static, IVDD = 0). IVCC and IVDD measured with 10.3 MHz analog input @ −0.5 dBFS.
AC SPECIFICATIONS
VDD = 3.3 V, VCC = 5 V; differential encode input, unless otherwise noted.
Table 2.
Test 105 MSPS
Parameter
Temp Level Min Typ Max
DYNAMIC PERFORMANCE1
Signal-to-Noise Ratio (SNR) (Without Harmonics)
fIN = 10.3 MHz
25°C I
66.5 68.0
fIN = 49 MHz
25°C I
65.5 67.5
fIN = 70 MHz
25°C V
67.0
fIN = 150 MHz
25°C V
65.4
fIN = 250 MHz
25°C V
63.7
Signal-to-Noise and Distortion (SINAD) Ratio
(with Harmonics)
fIN = 10.3 MHz
25°C I
66.0 68.0
fIN = 49 MHz
25°C I
64.0 67.5
fIN = 70 MHz
25°C V
66.9
fIN = 150 MHz
25°C V
64.0
fIN = 250 MHz
25°C V
61.2
Effective Number of Bits (ENOB)
fIN = 10.3 MHz
25°C I
11.1
fIN = 49 MHz
25°C I
11.0
fIN = 70 MHz
25°C V
10.9
fIN = 150 MHz
25°C V
10.4
fIN = 250 MHz
25°C V
9.9
Second-Order and Third-Order Harmonic
Distortion
fIN = 10.3 MHz
25°C I
−78 −85
fIN = 49 MHz
25°C I
−73 −80
fIN = 70 MHz
25°C V
−83
fIN = 150 MHz
25°C V
−72
fIN = 250 MHz
25°C V
−67
Worst Other Harmonic or Spur (Excluding
Second-Order and Third-Order Harmonics)
fIN = 10.3 MHz
25°C I
−88 −92
fIN = 49 MHz
25°C I
−82 −89
fIN = 70 MHz
25°C V
−87
fIN = 150 MHz
25°C V
−87
fIN = 250 MHz
25°C V
−85
Two-Tone Intermodulation Distortion (IMD3)
fIN1 = 49.3 MHz; fIN2 = 50.3 MHz
25°C V
−92
fIN1 = 150 MHz; fIN2 = 151 MHz
25°C V
−80
125 MSPS
Min Typ Max
66.0 67.7
64.0 66.0
65.4
62.0
60.0
65.0 67.0
63.5 65.5
64.5
61.5
57.7
10.9
10.7
10.6
10.0
9.4
−76 −85
−72 −76
−78
−67
−65
−84 −90
−82 −87
−85
−84
−76
−90
−76
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
1 SNR/harmonics based on an analog input voltage of −0.5 dBFS referenced to a 2 V full-scale input range. Harmonics are specified with the SFDR mode enabled
(SFDR MODE = 5 V). SNR/SINAD specified with the SFDR mode disabled (SFDR MODE = ground).
Rev. A | Page 4 of 20
5 Page 
AD9433
–95
WORST OTHER (dBc)
–90
THIRD HARMONIC (dBc)
–85
–80
SECOND HARMONIC (dBc)
–75
–70 SNR (dB)
–65
0
10 20 30 40 50 60 70 80 90
DUTY CYCLE HIGH (%)
Figure 16. Dynamic Performance vs. Encode Duty Cycle, fS = 105 MSPS,
fIN = 49.3 MHz, Differential AIN @ −0.5 dBFS, SFDR Mode Enabled
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
Figure 17. Integral Nonlinearity vs. Output Code with SFDR Mode Disabled
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
Figure 18. Differential Nonlinearity vs. Output Code
300 18
280 15
260 12
ICC (mA)
240 9
220 6
IDD (mA)
200 3
180
0
25 50 75 100
ENCODE FREQUENCY (MHz)
0
125
Figure 19. IDD and ICC vs. Encode Rate, fIN = 10.3 MHz,
Differential AIN @ −0.5 dBFS
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
Figure 20. Integral Nonlinearity vs. Output Code with SFDR Mode Enabled
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
7.68
15.36
23.04
FREQUENCY (MHz)
30.72
Figure 21. FFT: fS = 61.44 MSPS, fIN = 46.08 MHz, Four WCDMA Carriers,
Differential AIN, SFDR Mode Enabled
Rev. A | Page 10 of 20
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet AD9433.PDF ] | |
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