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PDF ADG1202 Data sheet ( Hoja de datos )
| Número de pieza | ADG1202 | |
| Descripción | iCMOS SPST | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Low Capacitance, Low Charge Injection,
±15 V/+12 V iCMOS SPST in SOT-23
ADG1201/ADG1202
FEATURES
2.4 pF off capacitance
<1 pC charge injection
Low leakage; 0.6 nA maximum @ 85°C
120 Ω on resistance
Fully specified at ±15 V, +12 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
6-lead SOT-23 package
APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems
GENERAL DESCRIPTION
The ADG1201/ADG1202 are monolithic complementary
metal-oxide semiconductor (CMOS) devices containing
an SPST switch designed in an iCMOS® (industrial CMOS)
process. iCMOS is a modular manufacturing process
combining high voltage CMOS and bipolar technologies.
It enables the development of a wide range of high perform-
ance analog ICs capable of 33 V operation in a footprint
that no previous generation of high voltage parts has been
able to achieve. Unlike analog ICs using conventional
CMOS processes, iCMOS components can tolerate high
supply voltages while providing increased performance,
dramatically lower power consumption, and reduced
package size.
The ultralow capacitance and charge injection of these
switches make them ideal solutions for data acquisition
and sample-and-hold applications, where low glitch and fast
settling are required. Fast switching speed coupled with
high signal bandwidth make the parts suitable for video
signal switching.
FUNCTIONAL BLOCK DIAGRAM
ADG1201
ADG1202
S DS D
IN IN
SWITCHES SHOWN FOR A LOGIC “1” INPUT
Figure 1.
iCMOS construction ensures ultralow power dissipation,
making the parts ideally suited for portable and battery-
powered instruments.
The ADG1201/ADG1202 contain a single-pole/single-throw
(SPST) switch. Figure 1 shows that with a logic input of 1, the
switch of the ADG1201 is closed and that of the ADG1202 is
open. Each switch conducts equally well in both directions when
on and has an input signal range that extends to the supplies. In
the off condition, signal levels up to the supplies are blocked.
PRODUCT HIGHLIGHTS
1. Ultralow capacitance.
2. <1 pC charge injection.
3. Ultralow leakage.
4. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V.
5. No VL logic power supply required.
6. SOT-23 package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Peak Current, S or D
Continuous Current per
Channel, S or D
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
6 Lead SOT-23
θJA,Thermal Impedance
θJC, Thermal Impedance
Reflow Soldering Peak
Temperature, Pb-free
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS – 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
GND – 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
100 mA (pulsed at 1 ms, 10%
duty cycle maximum)
30 mA
−40°C to +125°C
−65°C to +150°C
150°C
229.6°C/W
91.99°C/W
260°C
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
ADG1201/ADG1202
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 16
5 Page 
ADG1201/ADG1202
VDD
0.1µF
VSS
0.1µF
VDD
VSS
VIN ADG1201 50%
50%
S
VS IN
D VOUT
VIN ADG1202 50%
50%
RL CL
300Ω
35pF
VOUT
90%
90%
GND
tON tOFF
Figure 26. Switching Times
VDD
VSS
VDD
VSS
RS S
D
VS IN
GND
VOUT
CL
1nF
VIN ADG1201
ON
OFF
VIN ADG1202
VOUT
QINJ = CL × ΔVOUT
ΔVOUT
Figure 27. Charge Injection
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADG1202.PDF ] | |
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