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HI-1567 PDF даташит

Спецификация HI-1567 изготовлена ​​​​«HOLTIC» и имеет функцию, называемую «5V Monolithic Dual Transceivers».

Детали детали

Номер произв HI-1567
Описание 5V Monolithic Dual Transceivers
Производители HOLTIC
логотип HOLTIC логотип 

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HI-1567 Даташит, Описание, Даташиты
July 2016
HI-1567, HI-1568
MIL-STD-1553 / 1760
5V Monolithic Dual Transceivers
DESCRIPTION
PIN CONFIGURATIONS
The HI-1567 and HI-1568 are low power CMOS dual
transceivers designed to meet the requirements of
MIL-STD-1553 and MIL-STD-1760 specifications.
The transmitter section of each bus takes complementary
CMOS / TTL Manchester II bi-phase data and converts it to
differential voltages suitable for driving the bus isolation
transformer. Separate transmitter inhibit control signals
are provided for each transmitter.
The receiver section of each bus converts the 1553 bus bi-
phase data to complementary CMOS / TTL data suitable
for input to a Manchester decoder. Each receiver has a
separate enable input which can be used to force the
output of the receiver to a logic 0 (HI-1567) or logic 1 (HI-
1568).
To minimize the package size for this function, the
transmitter outputs are internally connected to the receiver
inputs, so that only two pins are required for connection to
each coupling transformer.
FEATURES
! Compliant to MIL-STD-1553A & B,
MIL-STD-1760, ARINC 708A
! CMOS technology for low standby power
! Smallest footprint available in 44-pin plastic
chip-scale package with integral heatsink
! Less than 1.0W maximum power dissipation
! Also available in DIP and small outline
(ESOIC) package options
! Industrial and extended temperature ranges
! Industry standard pin configurations
N/C 1
RXENA 2
GNDA 3
GNDA 4
GNDA 5
VDDB 6
VDDB 7
BUSB 8
BUSB 9
BUSB 10
BUSB 11
1567PCI
1567PCT
1568PCI
1568PCT
33 N/C
32 N/C
31 TXINHA
30 RXA
29 RXA
28 N/C
27 N/C
26 TXB
25 TXB
24 TXINHB
23 N/C
44 Pin Plastic 7mm x 7mm
Chip-scale package
VDDA 1
BUSA 2
BUSA 3
RXENA 4
GNDA 5
VDDB 6
BUSB 7
BUSB 8
RXENB 9
GNDB 10
1567PSI
1567PST
1567PSM
1568PSI
1568PST
1568PSM
20 TXA
19 TXA
18 TXINHA
17 RXA
16 RXA
15 TXB
14 TXB
13 TXINHB
12 RXB
11 RXB
20 Pin Plastic ESOIC - WB package
VDDA 1
BUSA 2
BUSA 3
RXENA 4
GNDA 5
VDDB 6
BUSB 7
BUSB 8
RXENB 9
GNDB 10
1567CDI
1567CDT
1567CDM
1568CDI
1568CDT
1568CDM
20 TXA
19 TXA
18 TXINHA
17 RXA
16 RXA
15 TXB
14 TXB
13 TXINHB
12 RXB
11 RXB
20 Pin Ceramic DIP package
(DS1567 Rev. T)
HOLT INTEGRATED CIRCUITS
www.holtic.com
07/16









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HI-1567 Даташит, Описание, Даташиты
HI-1567, HI-1568
PIN DESCRIPTIONS
PIN
(DIP/ESOIC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SYMBOL
VDDA
BUSA
BUSA
RXENA
GNDA
VDDB
BUSB
BUSB
RXENB
GNDB
RXB
RXB
TXINHB
TXB
TXB
RXA
RXA
TXINHA
TXA
TXA
FUNCTION
power supply
analog
analog
digital input
power supply
power supply
analog
analog
digital input
power supply
digital output
digital output
digital input
digital input
digital input
digital output
digital output
digital input
digital input
digital input
DESCRIPTION
+5 volt power for bus A
MIL-STD-1533 bus driver A, positive signal
MIL-STD-1553 bus driver A, negative signal
Receiver A enable. If low, forces RXA and RXA low (HI-1567) or High (HI-1568)
Ground for bus A
+5 volt power for bus B
MIL-STD-1533 bus driver B, positive signal
MIL-STD-1553 bus driver B, negative signal
Receiver B enable. If low, forces RXB and RXB low (HI-1567) or High (HI-1568)
Ground for bus B
Receiver B output, inverted
Receiver B output, non-inverted
Transmit inhibit, bus B. If high BUSB, BUSB disabled
Transmitter B digital data input, non-inverted
Transmitter B digital data input, inverted
Receiver A output, inverted
Receiver A output, non-inverted
Transmit inhibit, bus A. If high BUSA, BUSA disabled
Transmitter A digital data input, non-inverted
Transmitter A digital data input, inverted
FUNCTIONAL DESCRIPTION
The HI-1567 family of data bus transceivers contains differ-
ential voltage source drivers and differential receivers. It is in-
tended for applications using a MIL-STD-1553 A/B data bus.
The device produces a trapezoidal output waveform during
transmission.
TRANSMITTER
Data input to the device’s transmitter section is from the com-
plementary CMOS /TTL inputs TXA/B and TXA/B. The
transmitter accepts Manchester II bi-phase data and con-
verts it to differential voltages on BUSA/B and BUSA/B. The
transceiver outputs are either direct- or transformer-coupled
to the MIL-STD-1553 data bus. Both coupling methods pro-
duce a nominal voltage on the bus of 7.5 volts peak to peak.
comparator that produces CMOS/TTL data at the RXA/B
and RXA/B output pins. When the MIL-STD-1553 bus is idle
and RXENA or RXENB are high, RXA/B will be logic “0” on
HI-1567 and logic “1” on HI-1568.
The receiver outputs are forced to the bus idle state (logic “0”
for HI-1567 or logic “1” for HI-1568) when RXENA or RXENB
is low.
MIL-STD-1553 BUS INTERFACE
A direct-coupled interface (see Figure 2) uses a 1:2.5 ratio
isolation transformer and two 55 ohm isolation resistors
between the transformer and the bus. The primary center-
tap of the isolation transformer must be connected to GND.
The transmitter is automatically inhibited and placed in the
high impedance state when both TXA/B and TXA/B are
driven with the same logic state. A logic “1” applied to the
TXINHA/B input forces the transmitter to the high impedance
state, regardless of the state of TXA/B and TXA/B.
RECEIVER
The receiver accepts bi-phase differential data from the MIL-
STD-1553 bus through the same direct- or transformer-
coupled interface as the transmitter. The receiver’s differen-
tial input stage drives a filter and threshold
In a transformer-coupled interface (see Figure 2), the
transceiver is connected to a 1:1.79 isolation transformer
which in turn is connected to a 1:1.4 coupling transformer.
The transformer coupled method also requires two coupling
resistors equal to 75% of the bus characteristic impedence
(Zo) between the coupling transformer and the bus.
Figure 3 and Figure 4 show test circuits for measuring
electrical characteristics of both direct- and transformer-
coupled interfaces respectively. (See electrical
characteristics on the following pages).
HOLT INTEGRATED CIRCUITS
2









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HI-1567 Даташит, Описание, Даташиты
HI-1567, HI-1568
TXA/B
TXA/B
TXINHA/B
RXA/B
RXA/B
RXENA/B
Each Bus
TRANSMITTER
Transmit
Logic
Slope
Control
Data Bus
Isolation
Transformer
BUSA/B
Coupler
Network
Direct or
Transformer
BUSA/B
RECEIVER
Receive
Logic
Comparator
Input
Filter
Figure 1. Block Diagram
TRANSMIT WAVEFORM - EXAMPLE PATTERN
TXA/B
TXA/B
BUSA/B - BUSA/B
Vin
(Line to Line)
RXA/B (HI-1567)
RXA/B (HI-1567)
RXA/B (HI-1568)
RXA/B (HI-1568)
tDR
RECEIVE WAVEFORMS - EXAMPLE PATTERN
tDR
tRG
tDR
tRG
tRG tRG
HOLT INTEGRATED CIRCUITS
3
tDR










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