5P49V6914 PDF даташит
Спецификация 5P49V6914 изготовлена «IDT» и имеет функцию, называемую «Programmable Clock Generator». |
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Детали детали
Номер произв | 5P49V6914 |
Описание | Programmable Clock Generator |
Производители | IDT |
логотип |
30 Pages
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Programmable Clock Generator
5P49V6914
DATASHEET
Description
Features
The 5P49V6914 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock® 6).
The frequencies are generated from a single reference clock.
The reference clock can come from one of the two redundant
clock inputs. A glitchless manual switchover function allows
one of the redundant clocks to be selected during normal
operation.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
CLKIN
CLKINB
XOUT
XIN/REF
VDDA
CLKSEL
1 24 23
22
21
20
19
18
2 17
3
EPAD
16
4
GND
15
5 14
6 13
7 8 9 10 11 12
VDDO2
OUT2
OUT2B
VDDO3
OUT3
OUT3B
24-pin VFQFPN
• Generates up to three independent output frequencies
• High performance, low phase noise PLL, <0.5 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
• Three fractional output dividers (FODs)
• Independent Spread Spectrum capability on each output
pair
• Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
• I2C serial programming interface
• One reference LVCMOS output clock
• Three universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
• I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os - LVPECL, LVDS and HCSL
• Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to
200MHz
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 1MHz to 350MHz
– Crystal frequency range: 8MHz to 40MHz
• Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LVDS, LVPECL, HCSL Differential Clock Outputs –
1MHz to 350MHz
• Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
• Redundant clock inputs with manual switchover
• Programmable loop bandwidth
• Programmable slew rate control
• Programmable crystal load capacitance
• Individual output enable/disable
• Power-down mode
• 1.8V, 2.5V or 3.3V core VDDD, VDDA
• Available in 24-pin VFQFPN 4mm x 4mm package
• -40° to +85°C industrial temperature operation
5P49V6914 NOVEMBER 11, 2016
1 ©2016 Integrated Device Technology, Inc.
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5P49V6914 DATASHEET
Functional Block Diagram
XIN/REF
XOUT
CLKIN
CLKINB
CLKSEL
SD/OE
SEL1/SDA
SEL0/SCL
VDDA
VDDD
OTP
and
Control Logic
Applications
• Ethernet switch/router
• PCI Express 1.0/2.0/3.0
• Broadcast video/audio timing
• Multi-function printer
• Processor and FPGA clocking
• Any-frequency clock conversion
• MSAN/DSLAM/PON
• Fiber Channel, SAN
• Telecom line cards
• 1 GbE and 10 GbE
PLL
FOD1
FOD2
FOD3
PROGRAMMABLE CLOCK GENERATOR
2
VDDO0
OUT0_SEL_I2CB
VDDO1
OUT1
OUT1B
VDDO2
OUT2
OUT2B
VDDO3
OUT3
OUT3B
NOVEMBER 11, 2016
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5P49V6914 DATASHEET
Table 1: Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Name
CLKIN
CLKINB
XOUT
XIN/REF
VDDA
CLKSEL
SD/OE
SEL1/SDA
SEL0/SCL
VDDA
NC
NC
OUT3B
OUT3
VDDO3
OUT2B
OUT2
VDDO2
OUT1B
OUT1
VDDO1
VDDD
Type
Input
Internal
Pull-down
Input
Internal
Pull-down
Input
Input
Power
Input
Internal
Pull-down
Input
Internal
Pull-down
Input
Input
Internal
Pull-down
Internal
Pull-down
Power
––
––
Output
Output
Power
Output
Output
Power
Output
Output
Power
Power
Description
Differential clock input. Weak 100kohms internal pull-down.
Complementary differential clock input. Weak 100kohms internal pull-down.
Crystal Oscillator interface output.
Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure that
the input voltage is 1.2V max.Refer to the section “Overdriving the XIN/REF
Interface”.
Analog functions power supply pin.Connect to 1.8V to 3.3V. VDDA and VDDD should
have the same voltage applied.
Input clock select. Selects the active input reference source in manual switchover
mode.
0 = XIN/REF, XOUT (default)
1 = CLKIN, CLKINB
CLKSEL Polarity can be changed by I2C programming as shown in Table 4.
Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit
controls the configuration of the SD/OE pin. The SH bit needs to be high for SD/OE
pin to be configured as SD. The SP bit (0x02) controls the polarity of the signal to be
either active HIGH or LOW only when pin is configured as OE (Default is active
LOW.) Weak internal pull down resistor. When configured as SD, device is shut
down, differential outputs are driven high/low, and the single-ended LVCMOS
outputs are driven low. When configured as OE, and outputs are disabled, the
outputs can be selected to be tri-stated or driven high/low, depending on the
programming bits as shown in the SD/OE Pin Function Truth table.
Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB. Weak
internal pull down resistor.
Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB. Weak
internal pull down resistor.
Analog functions power supply pin.Connect to 1.8V to 3.3V. VDDA and VDDD should
have the same voltage applied.
No connect.
No connect.
Complementary Output Clock 3. Please refer to the Output Drivers section for more
details.
Output Clock 3. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT3/OUT3B.
Complementary Output Clock 2. Please refer to the Output Drivers section for more
details.
Output Clock 2. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT2/OUT2B.
Complementary Output Clock 1. Please refer to the Output Drivers section for more
details.
Output Clock 1. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT1/OUT1B.
Digital functions power supply pin. Connect to 1.8 to 3.3V. VDDA and VDDD should
have the same voltage applied.
NOVEMBER 11, 2016
3 PROGRAMMABLE CLOCK GENERATOR
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