8T39S04A PDF даташит
Спецификация 8T39S04A изготовлена «IDT» и имеет функцию, называемую «Crystal or Differential to Differential Clock Fanout Buffer». |
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Детали детали
Номер произв | 8T39S04A |
Описание | Crystal or Differential to Differential Clock Fanout Buffer |
Производители | IDT |
логотип |
30 Pages
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Crystal or Differential to
Differential Clock Fanout Buffer
8T39S04A
Datasheet
General Description
The 8T39S04A is a high-performance clock fanout buffer. The input
clock can be selected from two differential inputs or one crystal input.
The internal oscillator circuit is automatically disabled if the crystal
input is not selected. The crystal pin can be driven by a single-ended
clock.The selected signal is distributed to four differential outputs
which can be configured as LVPECL, LVDS or HSCL outputs. In
addition, an LVCMOS output is provided. All outputs can be disabled
into a high-impedance state. The device is designed for a signal
fanout of high-frequency, low phase-noise clock and data signal. The
outputs are at a defined level when inputs are open or tied to ground.
It is designed to operate from a 3.3V or 2.5V core power supply, and
either a 3.3V or 2.5V output operating supply.
Block Diagram
PullDown
PullDown
Features
• Two differential reference clock input pairs
• Differential input pairs can accept the following input levels:
LVPECL, LVDS, HCSL, HSTL and Single-ended
• Crystal Oscillator Interface
• Crystal input frequency range: 10MHz to 40MHz
• Maximum Output Frequency
LVPECL - 2GHz
LVDS - 2GHz
HCSL - 250MHz
LVCMOS - 250MHz
• Two banks, each has two differential output pairs that can be
configured as LVPECL or LVDS or HCSL
• One single-ended reference output with synchronous enable to
avoid clock glitch
• Output skew: 80ps (maximum), Bank A and Bank B at the same
output level
• Part-to-part skew: 200ps (typical), design target
• Additive RMS phase jitter @ 156.25MHz, (12kHz - 20MHz):
34.7fs (typical), 3.3V/ 3.3V
• Supply voltage modes:
VDD/VDDO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Pin Assignment
REFOUT
24 23 22 21 20 19 18 17
nc 25
16
nCLK1 26
15
CLK1 27
14
VDD 28
REFOUT 29
8T39S04A
13
12
VDDOREF 30
11
OE_SE 31
10
SMODE1 32
9
12345678
REF_SEL1
nCLK0
CLK0
REF_SEL0
XTAL_OUT
XTAL_IN
VDD
SMODE0
©2016 Integrated Device Technology, Inc.
32-pin, 5mm x 5mm VFQFN Package
1 May 20, 2016
No Preview Available ! |
8T39S04A Datasheet
Pin Description and Pin Characteristic Table
Table 1. Pin Descriptions
Number
Name
Type
Description
1
GND
Power
2
VDDOA
Power
3
QA0
Output
4
nQA0
Output
Power supply ground.
Output supply pin for Bank QA outputs.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
5
VDDOA
Power
6
QA1
Output
Output supply pin for Bank QA outputs.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
7
nQA1
Output
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
8
GND
Power
Power supply ground.
9
SMODE0
Input
Pulldown
Output driver select for Bank A and Bank B outputs. See Table 3D for function.
LVCMOS/LVTTL interface levels.
10 VDD Power
11
XTAL_IN
Input
Power supply pin.
Crystal oscillator interface.
12 XTAL_OUT Output
Crystal oscillator interface.
13
REF_SEL0
Input
Pulldown
Input clock selection. LVCMOS/LVTTL interface levels.
See Table 3A for function.
14
CLK0
Input
Pullup/
Pulldown
Non-inverting differential clock. Internally biased to 0.33VDD.
15
nCLK0
Input
Pullup/
Pulldown
Inverting differential clock. Internal resistor bias to 0.4VDD.
16
REF_SEL1
Input
Pulldown
Input clock selection. LVCMOS/LVTTL interface levels.
See Table 3A for function.
17
GND
Power
18
nQB1
Output
Power supply ground.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
19
QB1
Output
20
VDDOB
Power
21
nQB0
Output
22
QB0
Output
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pin for Bank QB outputs.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
23
VDDOB
Power
24
GND
Power
25 nc Unused
Output supply pin for Bank QB outputs.
Power supply ground.
No connect pin.
26
nCLK1
Input
Pullup/
Pulldown
Inverting differential clock. Internal resistor bias to 0.4VDD.
27
CLK1
Input
Pullup/
Pulldown
Non-inverting differential clock. Internally biased to 0.33VDD.
28 VDD Power
29
REFOUT
Output
Power supply pin.
Single-ended reference clock output. LVCMOS/LVTTL interface levels.
30
VDDOREF
Power
Output supply pin for REFOUT output.
31
OE_SE
Input
Pulldown Output enable. LVCMOS/LVTTL interface levels. See Table 3B.
32
SMODE1
Input
Pulldown
Output driver select for Bank A and Bank B outputs. See Table 3D for function.
LVCMOS/LVTTL interface levels.
0
ePAD
Power
Connect ePAD to ground to ensure proper heat dissipation.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2016 Integrated Device Technology, Inc.
2
May 20, 2016
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Table 2. Pin Characteristics
Symbol
CIN
RPULLDOWN
RPULLUP
CPD
Parameter
Input
Capacitance
OE_SE,
SMODE[1:0],
REF_SEL[1:0]
Input Pulldown Resistor
Input Pullup CLK0, CLK1
Resistor
nCLK0, nCLK1
Power
Dissipation REFOUT
Capacitance
ROUT
Output
Impedance
REFOUT
Test Conditions
VDDOREF = 3.465V
VDDOREF = 2.625V
VDDOREF = 3.3V
VDDOREF = 2.5V
8T39S04A Datasheet
Minimum
Typical
2
50
100
75
5.3
6.3
52
63
Maximum
Units
pF
k
k
k
pF
pF
©2016 Integrated Device Technology, Inc.
3
May 20, 2016
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