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87972I-147 PDF даташит

Спецификация 87972I-147 изготовлена ​​​​«IDT» и имеет функцию, называемую «1-to-12 LVCMOS/LVTTL Clock Multiplier/Zero Delay Buffer».

Детали детали

Номер произв 87972I-147
Описание 1-to-12 LVCMOS/LVTTL Clock Multiplier/Zero Delay Buffer
Производители IDT
логотип IDT логотип 

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87972I-147 Даташит, Описание, Даташиты
Low Skew, 1-to-12 LVCMOS/LVTTL
Clock Multiplier/Zero Delay Buffer
87972I-147
Datasheet
General Description
The 87972I-147 is a low skew, LVCMOS/LVTTL Clock Generator
and a member of the family of High Performance Clock Solutions
from IDT. The 87972I-147 has three selectable inputs and
provides 14 LVCMOS/LVTTL outputs.
The 87972I-147 is a highly flexible device. Using the crystal
oscillator input, it can be used to generate clocks for a system. All
of these clocks can be the same frequency or the device can be
configured to generate up to three different frequencies among the
three output banks. Using one of the single ended inputs, the
87972I-147 can be used as a zero delay buffer/multiplier/ divider in
clock distribution applications.
The three output banks and feedback output each have their own
output dividers which allows the device to generate a multitude of
different bank frequency ratios and output-to-input frequency
ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be select-
ed to be inverting or non-inverting. The output frequency range is
10MHz to 150MHz. Input frequency range is 6MHz to 150MHz.
The 87972I-147 also has a QSYNC output which can be used or
system synchronization purposes. It monitors Bank A and Bank C
outputs and goes low one period of the faster clock prior to
coincident rising edges of Bank A and Bank C clocks. QSYNC
then goes high again when the coincident rising edges of Bank A
and Bank C occur. This feature is used primarily in applications
where Bank A and Bank C are running at different frequencies,
and is particularly useful when they are running at non-integer
multiples of one another.
Example Applications:
1.System Clock generator: Use a 16.66 MHz Crystal to generate
eight 33.33MHz copies for PCI and four 100MHz copies for the
CPU or PCI-X.
2.Line Card Multiplier: Multiply 19.44MHz from a back plane to
77.76MHz for the line Card ASICs and Serdes.
3.Zero Delay buffer for Synchronous memory: Fan out up to
twelve 100MHz copies from a memory controller reference
clock to the memory chips on a memory module with zero delay.
Features
Fully integrated PLL
Fourteen LVCMOS/LVTTL outputs; (12)clocks, (1)feedback,
(1)sync
Selectable crystal oscillator interface or LVCMOS/LVTTL
reference clock inputs
CLK0, CLK1 can accept the following input levels:
LVCMOS or LVTTL
Output frequency range: 10MHz to 150MHz
VCO range: 240MHz to 500MHz
Output skew: 200ps (maximum)
Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum)
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Compatible with PowerPC™and Pentium™Microprocessors
Available in lead-free (RoHS 6)packages.
Pin Assignment
39 38 37 36 35 34 33 32 31 30 29 28 27
FSEL_B1
FSEL_B0
FSEL_A1
FSEL_A0
QA3
VDDO
QA2
GNDO
QA1
VDDO
QA0
GNDO
VCO_SEL
40
41
42
43
44
45
46
47
48
49
50
51
52
1
26
25
24
23
22
21
20
19
18
17
16
15
14
2 3 4 5 6 7 8 9 10 11 12 13
FSEL_FB1
QSYNC
GNDO
QC0
VDDO
QC1
FSEL_C0
FSEL_C1
QC2
VDDO
QC3
GNDO
INV_CLK
©2015 Integrated Device Technology, Inc
87972I-147
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y Package
Top View
1 December 7, 2015









No Preview Available !

87972I-147 Даташит, Описание, Даташиты
Block Diagram
XTAL1
XTAL2
VCO_SEL Pullup
PLL_SEL Pullup
REF_SEL Pullup
CLK0 Pullup
CLK1 Pullup
CLK_SEL Pullup
EXT_FB Pullup
0
1
1
0
PHASE
DETECTOR
LPF
VCO
0
1
FSEL_FB2 Pullup
nMR/OE Pullup
POWER-ON
RESET
FSEL_A[0:1] Pullup
FSEL_B[0:1] Pullup
FSEL_C[0:1] Pullup
FSEL_FB[0:2] Pullup
FRZ_CLK Pullup
FRZ_DATA Pullup
INV_CLK Pullup
÷4, ÷6, ÷8, ÷12
÷4, ÷6, ÷8, ÷10
÷2, ÷4, ÷6, ÷8
2
÷4, ÷6, ÷8, ÷10
2
2 SYNC PULSE
3
DATA GENERATOR
0
÷2 1
OUTPUT DISABLE
CIRCUITRY
12
87972I-147 Datasheet
DQ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
DQ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
DQ
DQ
DQ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
QC0
QC1
QC2
QC3
QFB
DQ
SYNC
FRZ
QSYNC
©2015 Integrated Device Technology, Inc
2
December 7, 2015









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87972I-147 Даташит, Описание, Даташиты
87972I-147 Datasheet
Simplified Block Diagram
XTAL1
XTAL2
1
CLK0 Pullup
CLK1 Pullup
CLK_SEL Pullup
REF_SEL Pullup
EXT_FB Pullup
0
0
1
PLL
VCO RANGE
240MHz - 500MHz
VCO_SEL Pullup
PLL_SEL Pullup
nMR/OE
0
÷2 0
1
÷1 1
FSEL_A[0:1]
2
FSEL_
A1 A0
00
01
10
11
QAx
÷4
÷6
÷8
÷12
FSEL_B[0:1]
2
FSEL_
B1 B0
00
01
10
11
QBx
÷4
÷6
÷8
÷10
FRZ_CLK Pullup
FRZ_DATA Pullup
FSEL_C[0:1]
2
FSEL_
C1 C0
00
01
10
11
QCx
÷2
÷4
÷6
÷8
0
INV_CLK
1
FSEL_FB[0:2]
3
FSEL_
FB2 FB1 FB0 QFB
0 0 0 ÷4
0 0 1 ÷6
0 1 0 ÷8
0 1 1 ÷10
1 0 0 ÷8
1 0 1 ÷12
1 1 0 ÷16
1 1 1 ÷20
OUTPUT DISABLE
CIRCUITRY
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
QFB
QSYNC
©2015 Integrated Device Technology, Inc
3
December 7, 2015










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