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Número de pieza | 850S1201 | |
Descripción | 12:1 Single-ended Multiplexer | |
Fabricantes | IDT | |
Logotipo | ||
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No Preview Available ! 12:1 Single-ended Multiplexer
850S1201
Datasheet
General Description
The 850S1201 is a low skew12:1 Single-ended Clock Multiplexer.
The 850S1201 has 12 selectable single-ended clock inputs and 1
single- ended clock output. The device operates up to 250MHz and
is packaged in a 20 TSSOP package.
Features
• 12:1 single-ended multiplexer
• Nominal output impedance: 20 (VDD = 3.3V)
• Maximum output frequency: 250MHz
• Propagation delay: 2.7ns (maximum)
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
CLK_SEL0 Pulldown
CLK_SEL1 Pulldown
CLK_SEL2 Pulldown
CLK_SEL3 Pulldown
CLK0 Pulldown
CLK1 Pulldown
CLK10 Pulldown
CLK11 Pulldown
OE Pullup
Q
©2016 Integrated Device Technology, Inc.
1
Pin Assignment
CLK8
CLK9
CLK10
CLK11
VDD
CLK_SEL0
CLK_SEL1
CLK_SEL2
CLK_SEL3
OE
1
2
3
4
5
6
7
8
9
10
20 CLK7
19 CLK6
18 CLK5
17 CLK4
16 CLK3
15 CLK2
14 CLK1
13 CLK0
12 GND
11 Q
850S1201
20-Lead TSSOP
6.50mm x 4.40mm x 0.925mm
package body
G Package
Top View
Revison B, February 8, 2016
1 page 850S1201 Datasheet
Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum
VIH
Input
High Voltage
VIL
Input
Low Voltage
CLK[0:11],
IIH
Input
High Current
CLK_SEL[0:3]
OE
CLK[0:11],
IIL
Input
Low Current
CLK_SEL[0:3]
OE
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
VDD = 3.465V
VDD = 2.625V
VDD = 3.465V
VDD = 2.625V
VDD = VIN = 3.465V or 2.625V
VDD = VIN = 3.465V or 2.625V
VDD = 3.465V or 2.625V, VIN = 0V
VDD = 3.465V or 2.625V, VIN = 0V
VDD = 3.3V ± 5%, IOH = -12mA
VDD = 2.5V ± 5%, IOH = -12mA
VDD = 3.3V ± 5% or 2.5V ± 5%,
IOL = 12mA
2
1.7
-0.3
-0.3
-10
-150
2.6
1.8
VDD + 0.3
VDD + 0.3
0.8
0.7
150
10
0.5
NOTE 1: Output terminated with 50 to VDD/2. See Parameter Measurement Information section. Load Test Circuit diagrams.
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
fMAX
tpLH
Output Frequency
Propagation Delay, Low-to-High;
NOTE 1
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
155.52MHz, Integration
Range: 12kHz – 20MHz
tsk(i)
Input Skew
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle; NOTE 4
20% to 80%
f 200MHz
f = 250MHz
MUXISOLATION MUX Isolation
155.52MHz
Minimum
1.4
Typical
Maximum
250
2.7
Units
MHz
ns
0.35 ps
175 ps
600 ps
100 500 ps
46 54 %
40 60 %
43 dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
NOTE 4: Input duty cycle must be 50%.
©2016 Integrated Device Technology, Inc.
5
Revison B, February 8, 2016
5 Page 850S1201 Datasheet
Ordering Information
Table 8. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
850S1201BGILF
ICS0S1201BIL
“Lead-Free” 20 Lead TSSOP
Tube
-40C to 85C
850S1201BGILFT
ICS0S1201BIL
“Lead-Free” 20 Lead TSSOP
Tape & Reel
-40C to 85C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
©2016 Integrated Device Technology, Inc.
11
Revison B, February 8, 2016
11 Page |
Páginas | Total 13 Páginas | |
PDF Descargar | [ Datasheet 850S1201.PDF ] |
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