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831752 PDF даташит

Спецификация 831752 изготовлена ​​​​«IDT» и имеет функцию, называемую «Clock Switch».

Детали детали

Номер произв 831752
Описание Clock Switch
Производители IDT
логотип IDT логотип 

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831752 Даташит, Описание, Даташиты
Clock Switch for ATCA/AMC and PCIe
Applications
831752
Data Sheet
General Description
The 831752 is a high-performance, differential HCSL clock switch.
The device is designed for the routing of PCIe clock signals in
ATCA/AMC system and is optimized for PCIe Gen 1, Gen 2 and Gen
3. The device has one differential, bi-directional I/O (FCLK) for
connection to ATCA clock sources and to clock receivers through a
connector. The differential clock input CLK is the local clock input
and the HCSL output Q is the local clock output. In the common
clock mode, FCLK serves as an input and is routed to the differential
HCSL output Q. There are two local clock modes. In the local clock
mode 0, CLK is the input, Q is the clock output and FCLK is in
high-impedance state. In the local clock mode 1, CLK is the input
and both Q and FCLK are the outputs of the locally generated PCIe
clock signal. The 831752 is characterized to operate from a 3.3V
power or 2.5V power supply. The 831752 supports the switching of
PCI Express (2.5 Gb/s), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) clock
signals.
Pin Assignment
Features
Clock switch for PCIe and ATCA/AMC applications
Supports local and common ATCA/AMC clock modes
Bi-directional clock I/O FCLK:
- When operating as an output, FCLK is a source-terminated
HCSL signal.
- When operating as an input, FCLK accepts HCSL, LVDS and
LVPECL levels.
Local clock input (CLK) accepts HCSL, LVDS and LVPECL
differential signals
Local HCSL clock output (Q)
Maximum input/output clock frequency: 500MHz
Maximum input/output data rate: 1000Mb/s (NRZ)
LVCMOS interface levels for the control inputs
PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter
compliant
Full 3.3V or 2.5V supply voltage
Lead-free (RoHS 6) 16-lead TSSOP package
-40°C to 85°C ambient operating temperature
DIR_SEL
nOEFCLK
VDD
FCLK
nFCLK
GND
CLK
nCLK
1
2
3
4
5
6
7
8
16 IREF
15 GND
14 VDD
13 Q
12 nQ
11 GND
10 VDD
9 nc
831752
16-lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package, Top View
Block Diagram
FCLK
nFCLK
50 50
22.33
22.33
CLK Pulldown
nCLK Pullup/Pulldown
nOEFCLK Pullup
DIR_SEL Pulldown
IREF
1=disable
1Q
nQ
0 50 50
©2016 Integrated Device Technology, Inc
1
Revision B June 28, 2016









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831752 Даташит, Описание, Даташиты
831752 Data Sheet
Table 1. Pin Descriptions
Number
Name
Type
Description
1
DIR_SEL
Input
Pulldown
Direction control for the FCLK I/O. Works in conjunction with nOEFCLK.
See Table 3 for function. LVCMOS/LVTTL interface levels.
2
3, 10, 14
nOEFCLK
VDD
Input
Power
4, 5 FCLK, nFCLK I/O
6, 11, 15
7
8
9
12, 13
16
GND
CLK
nCLK
nc
nQ, Q
IREF
Power
Input
Input
Unused
Output
Input
Pullup
Pulldown
Pulldown/Pullup
Output enable for the FCLK I/O output. Works in conjunction with
DIR_SEL. See Table 3 for function. LVCMOS/LVTTL interface levels.
Core and output power supply pin.
Differential I/O. Signal direction is controlled by DIR_SEL. Accepts
differential signals when operating as an input. Differential HCSL
signals when operating as an output. Internal source termination can be
disabled. See Table 3 for function.
Power supply ground.
Non-inverting input.
Inverting differential clock input.
No connect.
Differential output pair. HCSL interface levels.
An external fixed precision resistor (475) from this pin to ground
provides a reference current used for the differential current-mode Q
and FCLK outputs.
NOTE: Pullup and pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN Input Capacitance
RPULLDOWN Input Pulldown Resistor
RPULLUP
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. Direction Control Function Table
Input
Input
DIR_SEL nOEFCLK Operation
FCLK Function
0
0
Local clock mode 0. The input signal at CLK is routed to Differential HCSL output with internal 50source
both outputs Q and FCLK.
termination
0 (default)
1 (default)
Local clock mode 1. The input signal at CLK is routed to Output is disabled (high impedance). Internal 50
the output Q.
termination is disabled.
1
X
Common reference clock mode. FCLK is the clock input.
Q is the clock output.
Differential clock input. Internal 50source
termination is disabled as well as output driver and
22.33resistors.
NOTE: X = 0 or 1
©2016 Integrated Device Technology, Inc
2
Revision B June 28, 2016









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831752 Даташит, Описание, Даташиты
831752 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, VDD
Inputs, VI
Outputs, VO
Package Thermal Impedance, JA
Storage Temperature, TSTG
Rating
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
81.2°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
VDD Core Supply Voltage
3.135
2.375
3.3
2.5
IDD Power Supply Current
Maximum
3.465
2.625
64
Units
V
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VIH Input High Voltage
VDD = 3.3V
VDD = 2.5V
VIL Input Low Voltage
VDD = 3.3V
VDD = 2.5V
DIR_SEL
IIH
Input High Current
nOEFLCK
VDD = VIN = 2.625V or 3.465V
2
1.7
-0.3
-0.3
DIR_SEL
-5
IIL Input Low Current
VDD = 2.625V or 3.465V, VIN = 0V
nOEFLCK
-150
Table 4C. Differential DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Input
IIH
CLK, nCLK
High Current
VDD = VIN = 3.3V
IIL
VPP
VCMR
Input
Low Current
CLK
nCLK
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
VDD = 3.3V, VIN = 0V
VDD = 3.3V, VIN = 0V
-5
-150
0.15
0.5
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Maximum
VDD + 0.3
VDD + 0.3
0.8
0.7
150
5
Maximum
150
1.3
VDD – 0.85
Units
V
V
V
V
µA
µA
µA
µA
Units
µA
µA
µA
V
V
©2016 Integrated Device Technology, Inc
3
Revision B June 28, 2016










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