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PDF 9DML04 Data sheet ( Hoja de datos )
| Número de pieza | 9DML04 | |
| Descripción | 2:4 3.3V PCIe Clock Mux | |
| Fabricantes | IDT | |
| Logotipo |  |
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2:4 3.3V PCIe Clock Mux
9DML04
Description
The 9DML04 devices are 3.3V members of IDT's
Full-Featured PCIe family. The 9DML04 supports PCIe
Gen1-4 Common Clocked (CC), Separate Reference no
Spread (SRnS), and Separate Reference Independent
Spread (SRIS) architectures. The part provides a choice of
asynchronous and glitch-free switching modes, and offers a
choice of integrated output terminations providing direct
connection to 85 or 100 transmission lines. The
9DML04P1 can be factory programmed with a user-defined
power up default SMBus configuration.
Recommended Application
Servers, ATCA, ATE, Master/Slave applications
Output Features
• 4 – 1~200 MHz Low-Power HCSL (LP-HCSL) DIF pairs
• 9DML0441 default ZOUT = 100
• 9DML0451 default ZOUT = 85
• 9DML04P1 factory programmable defaults
Key Specifications
• PCIe Gen1-2-3-4 CC compliant
• PCIe Gen2-3 SRIS compliant
• DIF additive cycle-to-cycle jitter <1ps
• DIF output-to-output skew <50ps
• Additive phase jitter is <0.1ps rms for PCIe
• Additive phase jitter 160fs rms typ. @156.25M (1.5M to
10M)
Block Diagram
^OE(3:0)#
4
DIF_INA
DIF_INB
vSW_MODE
^SEL_A_B#
DATASHEET
Features/Benefits
• Direct connection to 100 (xx41) or 85 (xx51)
transmission lines; saves 16 resistors compared to
standard PCIe devices
• 76mW typical power consumption; eliminates thermal
concerns
• Spread Spectrum (SS) compatible; allows SS for EMI
reduction
• Customer defined power up default can be factory
programmed into P1 device; allows exact optimization to
customer requirements:
• control input polarity
• control input pull up/downs
• slew rate for each output
• differential output amplitude
• output impedance for each output
• OE# pins; support DIF power management
• HCSL-compatible differential inputs; can be driven by
common clock source
• Selectable asynchronous or glitch-free switching; allows
the mux to be selected at power up even if both inputs are
not running, then transition to glitch-free switching mode
• Space saving 24-pin 4x4mm VFQFPN; minimal board
space
DIF3
A DIF2
B DIF1
DIF0
Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9DML04 REVISION A 06/06/16
1 ©2015 Integrated Device Technology, Inc.
1 page  
9DML04 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DML04. These ratings, which are standard values
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VDDx
Input Voltage
VIN
Input High Voltage, SMBus VIHSMB
Storage Temperature
Ts
SMBus clock and data pins
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 4.6V.
MIN
-0.5
-65
2500
TYP
MAX
4.6
VDD+0.5
3.9
150
125
UNITS NOTES
V 1,2
V 1,3
V1
°C 1
°C 1
V1
Electrical Characteristics–Clock Input Parameters
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Input Common Mode
Voltage - DIF_IN
VCOM
Common Mode Input Voltage
150
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
VSWING
dv/dt
Differential value
Measured differentially
300
0.4
Input Leakage Current
IIN
VIN = VDD , VIN = GND
Input Duty Cycle dtin Measurement from differential wavefrom
Input Jitter - Cycle to Cycle JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
-5
45
0
TYP
MAX
900
8
5
55
125
UNITS NOTES
mV 1
mV
V/ns
uA
%
ps
1
1,2
1
1
Electrical Characteristics–Current Consumption
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Operating Supply Current
Powerdown Current
1 Input clock stopped.
IDD
IDDPD
VDD, All outputs active @100MHz
VDD, all outputs disabled
23
1.6
MAX
30
2.5
UNITS
mA
mA
NOTES
1
REVISION A 06/06/16
5 2:4 3.3V PCIE CLOCK MUX
5 Page 
9DML04 DATASHEET
Package Outline and Package Dimensions (NLG24), cont. Use 2.45mm SQ EPAD
REVISION A 06/06/16 11 2:4 3.3V PCIE CLOCK MUX
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet 9DML04.PDF ] | |
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