PDF 932SQ426 Data sheet ( Hoja de datos )

Número de pieza	932SQ426
Descripción	CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING
Fabricantes	IDT
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No Preview Available ! DATASHEET CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 932SQ426 General Description Features/Benefits The 932SQ426 is a CK420BQ derivative supporting Separate Reference no Spread (SRnS) PCIe clocking architectures. It uses a 25MHz crystal for maximum performance and has 100MHz outputs tuned for non-spreading applications to provide the most open eye diagram on PCIe links. • Non-spread 100MHz outputs/ Supports SRnS PCIe architectures • 64-pin TSSOP and VFQFPN packages; maximum space savings Key Specifications Recommended Application CK420BQ for SRnS applications Output Features • 11 - HCSL 100MHz outputs for SRnS • 4 - NS_SAS/SRC outputs • 4 - CPU outputs • 3 - SRC outputs • 1 - HCSL DOT96 output • 1 - 3.3V 48M output • 5 - 3.3V PCI outputs • 1 - 3.3V 14.318M output • Cycle to cycle jitter: CPU/SRC/NS_SRC/NS_SAS < 50ps • Phase jitter: PCIe Gen2 <3ps rms • Phase jitter: PCIe Gen3 <1ps rms • Phase jitter: QPI 9.6GB/s <0.2ps rms • Phase jitter: NS-SAS <0.4ps rms using raw phase data • Phase jitter: NS-SAS <1.3ps rms using Clk Jit Tool 1.6.4 Block Diagram X1_25 X2 Low Drift non-SS PLL <500ps LTJ Non-SS PLL CPU(3:0) SRC(2:0) /3 PCI(4:0) NS_SAS(1:0) NS_SRC(1:0) DOT96 48M Test_Sel Test_Mode CKPWRGD#/PD SMBDAT SMBCLK Logic 14.31818MHz Non-SS PLL REF14M IREF IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 1 932SQ426 REV C 022916 1 page 932SQ426 CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING Pin Configuration (VFQFPN) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GNDPCI 1 48 GNDCPU VDDPCI 2 47 VDDCPU PCI4_2x 3 46 CPU1T PCI3_2x 4 45 CPU1C PCI2_2x 5 44 CPU0T PCI1_2x 6 43 CPU0C PCI0_2x 7 42 GNDNS GNDPCI 8 VDDPCI 9 932SQ426 41 AVDD_NS_SAS 40 NS_SAS1T VDD48 10 39 NS_SAS1C 48M_2x 11 38 NS_SAS0T GND48 12 37 NS_SAS0C GND96 13 36 GNDNS DOT96T 14 35 VDDNS DOT96C 15 34 NS_SRC1T AVDD96 16 33 NS_SRC1C 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64-pin VFQFPN Note: Pins with ^ prefix have internal 120K pullup Pins with v prefix have internal 120K pulldowm IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 5 932SQ426 REV C 022916 5 Page 932SQ426 CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING Electrical Characteristics - Input/Supply/Common Parameters TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Ambient Operating Temperature Input High Voltage Input Low Voltage TCOM VIH VIL Commmercial range 0 Single-ended inputs, except SMBus, low threshold and tri-level inputs Single-ended inputs, except SMBus, low threshold and tri-level inputs 2.2 GND - 0.3 Single-ended inputs, IIN VIN = GND, VIN = VDD -5 Input Current Single-ended inputs. VIN = 0 V; Inputs with internal pull-up IINP resistors -200 VIN = VDD; Inputs with internal pull-down resistors Low Threshold Input- High Voltage Low Threshold Input- Low Voltage VIH_FS VIL_FS 3.3 V +/-5% 3.3 V +/-5% 0.7 VSS - 0.3 Input Frequency Pin Inductance Capacitance Fi Lpin CIN COUT Logic Inputs Output pin capacitance CINX X1 & X2 pins Clk Stabilization Tdrive_PD# TSTAB tDRVPD From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock Differential output enable after PD# de-assertion Tfall Trise SMBus Input Low Voltage SMBus Input High Voltage SMBus Output Low Voltage tF tR VILSMB VIHSMB VOLSMB Fall time of control inputs Rise time of control inputs @ IPULLUP 2.1 SMBus Sink Current IPULLUP @ VOL Nominal Bus Voltage VDDSMB 3V to 5V +/- 10% SCLK/SDATA Rise Time tRSMB (Max VIL - 0.15) to (Min VIH + 0.15) SCLK/SDATA Fall Time tFSMB (Min VIH + 0.15) to (Max VIL - 0.15) SMBus Operating Frequency fMAXSMB Maximum SMBus operating frequency 1Guaranteed by design and characterization, not 100% tested in production. 4 2.7 2Control input must be monotonic from 20% to 80% of input swing. 3Time from deassertion until outputs are >200 mV TYP 25 2.4 0.4 25.00 1.3 200 MAX 70 UNITS NOTES °C 1 VDD + 0.3 0.8 V V 5 uA 200 uA VDD + 0.3 V 0.35 7 5 5 5 V MHz nH pF pF pF 1.8 ms 2 1 1 1 1 2 300 us 5 ns 5 ns 0.8 V VDDSMB 0.4 5.5 1000 V V mA V ns 300 ns 100 kHz 1,3 1,2 1,2 1 1 1 IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 11 932SQ426 REV C 022916 11 Page

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