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PDF ADuC841 Data sheet ( Hoja de datos )
| Número de pieza | ADuC841 | |
| Descripción | MicroConverter 12-Bit ADCs and DACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
MicroConverter 12-Bit ADCs and DACs with
Embedded High Speed 62 kB Flash MCU
ADuC841/ADuC842/ADuC843
FEATURES
Pin compatible upgrade of ADuC812/ADuC831/ADuC832
Increased performance
Single-cycle 20 MIPS 8052 core
High speed 420 kSPS 12-bit ADC
Increased memory
Up to 62 kBytes on-chip Flash/EE program memory
4 kBytes on-chip Flash/EE data memory
In-circuit reprogrammable
Flash/EE, 100 year retention, 100 kCycle endurance
2304 bytes on-chip data RAM
Smaller package
8 mm × 8 mm chip scale package
52-lead PQFP—pin-compatible upgrade
Analog I/O
8-channel, 420 kSPS high accuracy, 12-bit ADC
On-chip, 15 ppm/°C voltage reference
DMA controller, high speed ADC-to-RAM capture
Two 12-bit voltage output DACs1
Dual output PWM ∑-∆ DACs
On-chip temperature monitor function
8052 based core
8051 compatible instruction set (20 MHz max)
High performance single-cycle core
32 kHz external crystal, on-chip programmable PLL
12 interrupt sources, 2 priority levels
Dual data pointers, extended 11-bit stack pointer
On-chip peripherals
Time interval counter (TIC)
UART, I2C®, and SPI® Serial I/O
Watchdog timer (WDT)
Power supply monitor (PSM)
Power
Normal: 4.5 mA @ 3 V (core CLK = 2.098 MHz)
Power-down: 10 μA @ 3 V2
Development tools
Low cost, comprehensive development system
incorporating nonintrusive single-pin emulation,
IDE based assembly and C source debugging
APPLICATIONS
Optical networking—laser power control
Base station systems
Precision instrumentation, smart sensors
Transient capture systems
DAS and communications systems
1 ADuC841/ADuC842 only.
2 ADuC842/ADuC843 only, ADuC841 driven directly by external crystal.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
ADuC841/ADuC842/ADuC843
12-BIT
DAC
BUF
DAC1
ADC0
ADC1
ADC5
ADC6
ADC7
MUX
T/H
TEMP
SENSOR
12-BIT ADC
HARDWARE
CALIBRATON
12-BIT
DAC
16-BIT
- DAC
16-BIT
- DAC
16-BIT
PWM
16-BIT
PWM
BUF
DAC1
MUX
PWM0
PWM1
INTERNAL
BAND GAP
VREF
PLL2
OSC
20 MIPS 8052 BASED MCU WITH ADDITIONAL
PERIPHERALS
62 kBYTES FLASH/EE PROGRAM MEMORY
4 kBYTES FLASH/EE DATA MEMORY
2304 BYTES USER RAM
3 16 BIT TIMERS POWER SUPPLY MON
1 REAL TIME CLOCK WATCHDOG TIMER
4 PARALLEL
PORTS
UART, I2 C, AND SPI
SERIAL I/O
CREF
XTAL1 XTAL2
Figure 1.
GENERAL DESCRIPTION
The ADuC841/ADuC842/ADuC8431 are complete smart
transducer front ends, that integrates a high performance self-
calibrating multichannel ADC, a dual DAC, and an optimized
single-cycle 20 MHz 8-bit MCU (8051 instruction set compatible)
on a single chip.
The ADuC841 and ADuC842 are identical with the exception
of the clock oscillator circuit; the ADuC841 is clocked directly
from an external crystal up to 20 MHz whereas the ADuC842
uses a 32 kHz crystal with an on-chip PLL generating a
programmable core clock up to 16.78 MHz.
The ADuC843 is identical to the ADuC842 except that the
ADuC843 has no analog DAC outputs.
The microcontroller is an optimized 8052 core offering up to
20 MIPS peak performance. Three different memory options
are available offering up to 62 kBytes of nonvolatile Flash/EE
program memory. Four kBytes of nonvolatile Flash/EE data
memory, 256 bytes RAM, and 2 kBytes of extended RAM are
also integrated on-chip.
1 Protected by U.S. Patent No. 5,969,657.
(continued on page 15)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
Parameter
LOGIC INPUTS4
INPUT VOLTAGES
All Inputs Except SCLOCK, SDATA, RESET, and
XTAL1
VINL, Input Low Voltage
VINH, Input High Voltage
SDATA
VINL, Input Low Voltage
VINH, Input High Voltage
SCLOCK and RESET ONLY4
(Schmitt-Triggered Inputs)
VT+
VT–
VT+ – VT–
CRYSTAL OSCILLATOR
Logic Inputs, XTAL1 Only
VINL, Input Low Voltage
VINH, Input High Voltage
XTAL1 Input Capacitance
XTAL2 Output Capacitance
MCU CLOCK RATE
DIGITAL OUTPUTS
Output High Voltage (VOH)
VDD = 5 V
0.8
2.0
0.8
2.0
1.3
3.0
0.8
1.4
0.3
0.85
0.8
3.5
18
18
16.78
20
2.4
4
Output Low Voltage (VOL)
ALE, Ports 0 and 2
Port 3
SCLOCK/SDATA
Floating State Leakage Current4
STARTUP TIME
At Power-On
From Idle Mode
From Power-Down Mode
Wake-up with INT0 Interrupt
Wake-up with SPI/I2C Interrupt
Wake-up with External RESET
After External RESET in Normal Mode
After WDT Reset in Normal Mode
0.4
0.2
0.4
0.4
±10
±1
500
100
150
150
150
30
3
ADuC841/ADuC842/ADuC843
VDD = 3 V Unit
Test Conditions/Comments
0.4 V max
2.0 V min
0.8 V max
2.0 V min
0.95 V min
0.25 V max
0.4 V min
1.1 V max
0.3 V min
0.85 V max
0.4 V typ
2.5 V typ
18 pF typ
18 pF typ
8.38
MHz max
ADuC842/ADuC843 Only
8.38
MHz max
ADuC841 Only
V min
VDD = 4.5 V to 5.5 V
V typ
ISOURCE = 80 μA
2.4 V min VDD = 2.7 V to 3.3 V
2.6 V typ ISOURCE = 20 μA
0.4
V max
ISINK = 1.6 mA
0.2 V typ ISINK = 1.6 mA
0.4
V max
ISINK = 4 mA
0.4
V max
ISINK = 8 mA, I2C Enabled
±10 μA max
±1 μA typ
At any core CLK
500 ms typ
100 μs typ
400 μs typ
400 μs typ
400 μs typ
30 ms typ
3
ms typ
Controlled via WDCON SFR
Rev. A | Page 5 of 95
5 Page 
Data Sheet
ADuC841/ADuC842/ADuC843
Pin No.
22
23
24
25
26
27
28
29
30
Mnemonic
Type1
P3.4/T0/PWMC/PWM0/EXTCLK I/O
P3.5/T1/CONVST
I/O
P3.6/WR
P3.7/RD
SCLOCK
SDATA/MOSI
P2.0/A8/A16
I/O
I/O
I/O
I/O
I/O
P2.1/A9/A17
I/O
P2.2/A10/A18
I/O
Description
Input/Output Port 3 (P3.4). Port 3 is a bidirectional port with internal pull-up
resistors. Port 3 pins that have 1s written to them are pulled high by the internal
pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins
being pulled externally low source current because of the internal pull-up resistors.
Timer/Counter 0 Input (T0).
PWM Clock Input (PWMC).
PWM 0 Voltage Output (PWM0). PWM outputs can be configured to use Port 2.6
and Port 2.7 or Port 3.4 and Port 3.3.
Input for External Clock Signal (EXTCLK). This pin function must be enabled via the
CFG842 register.
Input/Output Port 3 (P3.5). Port 3 is a bidirectional port with internal pull-up
resistors. Port 3 pins that have 1s written to them are pulled high by the internal
pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins
being pulled externally low source current because of the internal pull-up resistors.
Timer/Counter 1 Input (T1).
Active Low Convert Start Logic Input for the ADC Block When the External Convert
Start Function is Enabled (CONVST). A low to high transition on this input puts the
track-and-hold into hold mode and starts the conversion.
Input/Output Port 3 (P3.6). Port 3 is a bidirectional port with internal pull-up
resistors. Port 3 pins that have 1s written to them are pulled high by the internal
pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins
being pulled externally low source current because of the internal pull-up resistors.
Write Control Signal, Logic Output (WR). Latches the data byte from Port 0 into the
external data memory.
Input/Output Port 3 (P3.7). Port 3 is a bidirectional port with internal pull-up
resistors. Port 3 pins that have 1s written to them are pulled high by the internal
pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins
being pulled externally low source current because of the internal pull-up resistors.
Read Control Signal, Logic Output (RD). Enables the external data memory to Port 0.
Serial Clock Pin for I2C-Compatible Clock or for SPI Serial Interface Clock.
User Selectable, I2C Compatible, or SPI Data Input/Output Pin (SDATA).
SPI Master Output/Slave Input Data I/O Pin for SPI Interface (MOSI).
Input/Output Port 2 (P2.0). Port 2 is a bidirectional port with internal pull-up
resistors. Port 2 pins that have 1s written to them are pulled high by the internal
pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins
being pulled externally low source current because of the internal pull-up resistors.
External Memory Addresses (A8). Port 2 emits the middle order address byte
during accesses to the external 24-bit external data memory space.
External Memory Addresses (A16). Port 2 emits the high order address byte during
accesses to the external 24-bit external data memory space.
Input/Output Port 2 (P2.1). Port 2 is a bidirectional port with internal pull-up
resistors. Port 2 pins that have 1s written to them are pulled high by the internal
pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins
being pulled externally low source current because of the internal pull-up resistors.
External Memory Addresses (A9). Port 2 emits the middle order address byte
during accesses to the external 24-bit external data memory space.
External Memory Addresses (A17). Port 2 emits the high order address byte during
accesses to the external 24-bit external data memory space.
Input/Output Port 2 (P2.2). Port 2 is a bidirectional port with internal pull-up
resistors. Port 2 pins that have 1s written to them are pulled high by the internal
pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins
being pulled externally low source current because of the internal pull-up resistors.
External Memory Addresses (A10). Port 2 emits the middle order address byte
during accesses to the external 24-bit external data memory space.
External Memory Addresses (A18). Port 2 emits the high order address byte during
accesses to the external 24-bit external data memory space.
Rev. A | Page 11 of 95
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADuC841.PDF ] | |
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