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PDF CS4924 Data sheet ( Hoja de datos )

Número de pieza CS4924
Descripción Multi-Channel Digital Audio Decoders
Fabricantes Cirrus Logic 
Logotipo Cirrus Logic Logotipo



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No Preview Available ! CS4924 Hoja de datos, Descripción, Manual

CS4923/4/5/6/7/8/9
Multi-Channel Digital Audio Decoders
l CS4923/4/5/6/7/8 features
— Optional Virtual 3D Output
— Simulated Surround and Programmable Effects
— Real Time Autodetection of Dolby Digital®,
DTS®, MPEG Multi-Channel and PCM
— Flexible 6-channel master or slave output
l CS4923/4/5/6/7/8/9 features
— IEC60958/61937 transmitter for compressed-
data or linear-PCM output
— Dedicated 8 kilobyte input buffer
— DAC clock via analog phase-locked loop
— Dedicated byte wide or serial host interface
— Multiple compressed data input modes
— PES layer decode for A/V synchronization
— 96-kHz-capable PCM I/O, master or slave
— Optional external memory and auto-boot
— +3.3-V CMOS low-power, 44-pin package
l CS4923/4/5/6 features
— Capable of Dolby Digital® Group A Performance
— Dolby bass manager and crossover filters
— Dolby Surround Pro Logic® Decoding
l CS4925/7: MPEG-2 Multi-Channel Decoder
l CS4926/8: DTS Multi-Channel Decoder
l CS4929: AAC 2-Channel (Low Complexity)
and MPEG-2 Stereo Decoder
Description
The CS4923/4/5/6/7/8 is a family of multi-channel digital
audio decoders, with the exception of the CS4929 as the
only stereo digital audio decoder. The CS4923/4/5/6 are
designed for Dolby Digital and MPEG-2 Stereo decoding. In
addition the CS4925 adds MPEG-2 multi-channel decoding
capability and the CS4926 provides DTS decoding. The
CS4927 is an MPEG-2 multi-channel decoder and the
CS4928 is a DTS multi-channel decoder. The CS4929 is an
AAC 2-channel and MPEG-2 stereo decoder. Each one of
the CS4923/4/5/6/7/8/9 provides a complete and flexible
solution for multi-channel (or stereo in the case of the
CS4929) audio decoding in home A/V receiver/amplifiers,
DVD movie players, out-board decoders, laser-disc players,
HDTV sets, head-end decoders, set-top boxes, and similar
products.
Cirrus Logic’s Crystal Audio Division provides a complete set
of audio decoder and auxiliary audio DSP application
programs for various applications. For all complementary
analog and digital audio I/O, Crystal Audio also provides a
complete set of high-quality audio peripherals including:
multimedia CODECs, stereo A/D and D/A converters and
IEC60958 interfaces. Of special note, the CS4226 is a
complementary CODEC providing a digital receiver, stereo
A/D converters, and six 20-bit DACs in one package.
ORDERING INFORMATION
CS4923xx-CL 44-pin PLCC (xx = ROM revision)
CRD4923 Reference design with CS4226
CDB4923 Evaluation board
RESET
RD, WR, SCDIO,
DATA7:0,
R/W, DS, SCDOUT,
EMAD7:0,
EMOE, EMWR, PSEL, A0, A1, ABOOT,
GPIO7:0 CS GPIO11 GPIO10 GPIO9 SCCLK SCDIN INTREQ
EXTMEM,
GPIO8
CMPDAT,
SDATAN2
CMPCLK,
SCLKN2
CMPREQ,
LRCLKN2
SCLKN1,
STCCLK2
LRCLKN1
SDATAN1
CLKIN
CLKSEL
Compressed
Data Input
Interface
Framer
Shifter
Digital
Audio
Input
Interface
Input
Buffer
Controller
RAM Input
Buffer
PLL
Clock Manager
Parallel or Serial Host Interface
24-Bit
DSP Processing
RAM RAM
Program Data
Memory Memory
ROM ROM
Program Data
Memory Memory
STC
RAM
Output
Buffer
DD
DC
Output
Formatter
MCLK
SCLK
LRCLK
AUDATA[2.0]
XMT958
FILT2 FILT1 VA AGND
DGND[3:1] VD[3:1]
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 1999
(All Rights Reserved)
AUG ‘99
DS262F2
1

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CS4924 pdf
CS4923/4/5/6/7/8/9
SWITCHING CHARACTERISTICS—RESET
(TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)z
Parameter
Symbol
Min
RESET minimum pulse width low
Trstl 100
All bidirectional pins high-Z after RESET low
Trst2z
-
Configuration bits setup before RESET high
Trstsu
50
Configuration bits hold after RESET high
Trsthld
15
Max
Unit
- ns
50 ns
- ns
- ns
RESET
RD, WR,
PSEL, ABOOT
All Bidirectional
Outputs
Trst2z
Trstl
Trstsu Trsthld
Figure 1. RESET Timing
DS262F2
5

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CS4924 arduino
CS4923/4/5/6/7/8/9
A1:0
DATA7:0
CS
R/W
DS
Tmah
Tmas
Tmrwsu
Tmdhr
Tmdd
Tmcdr
Tmrpw
Tmdis
Tmrd
Tm rw hld
Tmrdtw
Figure 7. Motorola Parallel Host Mode Read Cycle
A1:0
Tmas
DATA7:0
CS
R/W
DS
Tmah
Tmdsu
Tmcdw
Tmrwsu
Tmdhw
Tmwpw
Tmwd
Tmrwhld
Tmwtrd
Figure 8. Motorola Parallel Host Mode Write Cycle
DS262F2
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