PDF 9DBV0231 Data sheet ( Hoja de datos )

Número de pieza	9DBV0231
Descripción	2-output 1.8V PCIe Gen1/2/3 Zero Delay / Fanout Buffer
Fabricantes	IDT
Logotipo
Hay una vista previa y un enlace de descarga de 9DBV0231 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas
No Preview Available ! 2-output 1.8V PCIe Gen1/2/3 Zero Delay / Fanout Buffer 9DBV0231 DATASHEET Description The 9DBV0231 is a member of IDT's 1.8V Very-Low-Power (VLP) PCIe family. The device has 2 output enables for clock management. Recommended Application 1.8V PCIe Gen1/2/3 Zero-Delay/Fan-out Buffer (ZDB/FOB) Output Features • 2 – 1-200MHz Low-Power (LP) HCSL DIF pairs Key Specifications • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew <50ps • DIF additive phase jitter is <100fs rms for PCIe Gen3 • DIF additive phase jitter <300fs rms (12k-20MHz) Block Diagram Features/Benefits • LP-HCSL outputs; save 4 resistors compared to standard HCSL outputs • 35mW typical power consumption in PLL mode; reduced thermal concerns • Spread Spectrum (SS) compatible; allows use of SS for EMI reduction • OE# pins; support DIF power management • HCSL compatible differential input; can be driven by common clock sources • SMBus-selectable features; optimize signal integrity to application • slew rate for each output • differential output amplitude • Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application • Outputs blocked until PLL is locked; clean system start-up • Device contains default configuration; SMBus interface not required for device control • 3.3V tolerant SMBus interface works with legacy controllers • Space saving 24-pin 4x4mm VFQFPN; minimal board space , vOE(1:0)# 2 CLK_IN CLK_IN# ^vHIBW_BYPM_LOBW# ^CKPWRGD_PD# SDATA_3.3 SCLK_3.3 SS- Compatible PLL CONTROL LOGIC DIF1 DIF0 9DBV0231 REVISION F 04/28/16 1 ©2016 Integrated Device Technology, Inc. 1 page 9DBV0231 DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9DBV0231. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBOL CONDITIONS 1.8V Supply Voltage VDDxx Applies to all VDD pins Input Voltage VIN Input High Voltage, SMBus VIHSMB Storage Temperature Ts SMBus clock and data pins Junction Temperature Tj Input ESD protection ESD prot Human Body Model 1Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. 3 Not to exceed 2.5V. MIN -0.5 -0.5 -65 2000 TYP MAX 2.5 VDD+0.5V 3.6V 150 125 UNITS V V V °C °C V NOTES 1,2 1, 3 1 1 1 1 Electrical Characteristics–Clock Input Parameters TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN Input Common Mode Voltage - DIF_IN Input Swing - DIF_IN Input Slew Rate - DIF_IN VCOM VSWING dv/dt Common Mode Input Voltage Differential value Measured differentially 150 300 0.4 Input Leakage Current IIN VIN = VDD , VIN = GND -5 Input Duty Cycle dtin Measurement from differential wavefrom 45 Input Jitter - Cycle to Cycle JDIFIn Differential Measurement 1 Guaranteed by design and characterization, not 100% tested in production. 2Slew rate measured through +/-75mV window centered around differential zero 0 TYP MAX UNITS NOTES 1000 mV 1 1450 8 5 55 125 mV V/ns uA % ps 1 1,2 1 1 REVISION F 04/28/16 5 2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER 5 Page 9DBV0231 DATASHEET SMBus Table: Output Enable Register 1 Byte 0 Name Control Function Type 0 Bit 7 Reserved Bit 6 Reserved Bit 5 DIF OE1 Output Enable RW Low/Low Bit 4 Reserved Bit 3 DIF OE0 Output Enable RW Low/Low Bit 2 Reserved Bit 1 Reserved Bit 0 Reserved 1. A low on these bits will overide the OE# pin and force the differential output Low/Low 1 Enabled Enabled Default 1 1 1 1 1 1 1 1 SMBus Table: PLL Operating Mode and Output Amplitude Control Register Byte 1 Name Control Function Type 0 1 Bit 7 Bit 6 PLLMODERB1 PLLMODERB0 PLL Mode Readback Bit 1 PLL Mode Readback Bit 0 R R See PLL Operating Mode Table Bit 5 PLLMODE_SWCNTRL Enable SW control of PLL Mode RW Values in B1[7:6] Values in B1[4:3] set PLL Mode set PLL Mode Bit 4 Bit 3 PLLMODE1 PLLMODE0 PLL Mode Control Bit 1 PLL Mode Control Bit 0 RW1 RW1 See PLL Operating Mode Table Bit 2 Reserved Bit 1 Bit 0 AMPLITUDE 1 AMPLITUDE 0 Controls Output Amplitude RW RW 00 = 0.6V 10= 0.8V 01 = 0.7V 11 = 0.9V 1. B1[5] must be set to a 1 for these bits to have any effect on the part. Default Latch Latch 0 0 0 1 1 0 SMBus Table: DIF Slew Rate Control Register Byte 2 Name Control Function Bit 7 Reserved Bit 6 Reserved Bit 5 SLEWRATESEL DIF1 Slew Rate Selection Bit 4 Reserved Bit 3 SLEWRATESEL DIF0 Slew Rate Selection Bit 2 Reserved Bit 1 Reserved Bit 0 Reserved Type RW RW 0 Slow setting Slow setting 1 Fast setting Fast setting Default 1 1 1 1 1 1 1 1 SMBus Table: Frequency Select Control Register Byte 3 Name Control Function Bit 7 Bit 6 Bit 5 FREQ_SEL_EN Reserved Reserved Enable SW selection of frequency Bit 4 FSEL1 Freq. Select Bit 1 Bit 3 FSEL0 Freq. Select Bit 0 Bit 2 Bit 1 Bit 0 SLEWRATESEL FB Reserved Reserved Adjust Slew Rate of FB 1. B3[5] must be set to a 1 for these bits to have any effect on the part. Type RW RW1 RW1 RW 01 SW frequency change disabled SW frequency change enabled See Frequency Select Table Slow setting Fast setting Default 1 1 0 0 0 1 1 1 Byte 4 is Reserved and reads back 'hFF REVISION F 04/28/16 11 2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER 11 Page

Páginas	Total 17 Páginas
PDF Descargar	[ Datasheet 9DBV0231.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
9DBV0231	2-output 1.8V PCIe Gen1/2/3 Zero Delay / Fanout Buffer	IDT

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar