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9DBU0731 PDF даташит

Спецификация 9DBU0731 изготовлена ​​​​«IDT» и имеет функцию, называемую «7 O/P 1.5V PCIe Gen1-2-3 Fan-out Buffer».

Детали детали

Номер произв 9DBU0731
Описание 7 O/P 1.5V PCIe Gen1-2-3 Fan-out Buffer
Производители IDT
логотип IDT логотип 

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9DBU0731 Даташит, Описание, Даташиты
7 O/P 1.5V PCIe Gen1-2-3 Fan-out Buffer
9DBU0731
DATASHEET
Description
The 9DBU0731 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. The device has 7 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Fan-out Buffer (FOB)
Output Features
7 – 1-167MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF additive cycle-to-cycle jitter <5ps
DIF output-to-output skew < 60ps
DIF additive phase jitter is <300fs rms for PCIe Gen3
DIF additive phase jitter <350s rms for SGMII
Block Diagram
vOE(6:0)#
7
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
Features/Benefits
LP-HCSL outputs; save 14 resistors compared to standard
HCSL outputs
36mW typical power consumption; eliminates thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins for each output; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Device contains default configuration; SMBus interface not
required for device operation
3.3V tolerant SMBus interface works with legacy controllers
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
` DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0731 REVISION C 04/22/15
1
©2015 Integrated Device Technology, Inc.









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9DBU0731 Даташит, Описание, Даташиты
9DBU0731 DATASHEET
Pin Configuration
40 39 38 37 36 35 34 33 32 31
vSADR_tri 1
30 NC
vOE6# 2
29 vOE3#
DIF6 3
28 DIF3#
DIF6# 4
VDDR1.5 5
9DBU0731
27 DIF3
26 VDDIO
CLK_IN 6
ePad is GND
25 VDDA1.5
CLK_IN# 7
24 vOE2#
GNDDIG 8
23 DIF2#
SCLK_3.3 9
22 DIF2
SDATA_3.3 10
21 vOE1#
11 12 13 14 15 16 17 18 19 20
SMBus Address Selection Table
40-VFQFPN, 5mm x 5mm 0.4mm pin pitch
^ prefix indicates internal Pull-Up Resistor
v prefix indicates Internal Pull-Down Resistor
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
Power Management Table
CKPWRGD_PD#
0
1
1
1
CLK_IN
X
Running
Running
Running
SMBus
OEx bit
X
0
1
1
OEx# Pin
X
X
0
1
DIFx
True O/P Comp. O/P
Low Low
Low Low
Running Running
Low Low
Power Connections
Pin Number
VDD
VDDIO
5
11
16,25,31
12,17,26,32,
39
GND
41
8
41
Description
Input
receiver
analog
Digital Power
DIF
outputs,Logic
7 O/P 1.5V PCIE GEN1-2-3 FAN-OUT BUFFER
2
REVISION C 04/22/15









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9DBU0731 Даташит, Описание, Даташиты
9DBU0731 DATASHEET
Pin Descriptions
PIN #
PIN NAME
1 vSADR_tri
2 vOE6#
3 DIF6
4 DIF6#
5 VDDR1.5
6 CLK_IN
7 CLK_IN#
8 GNDDIG
9 SCLK_3.3
10 SDATA_3.3
11 VDDDIG1.5
12 VDDIO
13 vOE0#
14 DIF0
15 DIF0#
16 VDD1.5
17 VDDIO
18 DIF1
19 DIF1#
20 NC
21 vOE1#
22 DIF2
23 DIF2#
24 vOE2#
25 VDDA1.5
26 VDDIO
27 DIF3
28 DIF3#
29 vOE3#
30 NC
31 VDD1.5
32 VDDIO
33 DIF4
34 DIF4#
35 vOE4#
36 DIF5
37 DIF5#
38 vOE5#
39 VDDIO
40 ^CKPWRGD_PD#
41 ePAD
PIN TYPE
DESCRIPTION
LATCHED Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
IN
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
IN 1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR 1.5V power for differential input clock (receiver). This VDD should be treated as an Analog
power rail and filtered appropriately.
IN True Input for differential reference clock.
IN Complementary Input for differential reference clock.
GND Ground pin for digital circuitry
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 1.5V digital power (dirty power)
PWR Power supply for differential outputs
IN Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR Power supply, nominally 1.5V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
N/A No Connection.
IN Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR 1.5V power for the PLL core.
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
N/A No Connection.
PWR Power supply, nominally 1.5V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
IN 1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high assertion. Low enters
IN Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal
pull-up resistor.
GND Connect paddle to ground.
REVISION C 04/22/15
3 7 O/P 1.5V PCIE GEN1-2-3 FAN-OUT BUFFER










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