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9DBU0631 PDF даташит

Спецификация 9DBU0631 изготовлена ​​​​«IDT» и имеет функцию, называемую «6 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB».

Детали детали

Номер произв 9DBU0631
Описание 6 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
Производители IDT
логотип IDT логотип 

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9DBU0631 Даташит, Описание, Даташиты
6 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
9DBU0631
DATASHEET
Description
The 9DBU0631 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. The device has 6 output enables for clock
management and 3 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
Output Features
6 – 1-167MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <60ps
DIF phase jitter is PCIe Gen1-2-3 compliant
DIF bypass mode additive phase jitter is <300fs rms for
PCIe Gen3
DIF bypass mode additive phase jitter <350fs rms for
12k-20MHz
Block Diagram
Features/Benefits
LP-HCSL outputs; save 12 resistors compared to standard
HCSL outputs
46mW typical power consumption in PLL mode; eliminates
thermal concerns
Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device control
3.3V tolerant SMBus interface works with legacy controllers
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
vOE(5:0)#
6
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0631 REVISION C 04/22/15
1
©2015 Integrated Device Technology, Inc.









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9DBU0631 Даташит, Описание, Даташиты
9DBU0631 DATASHEET
Pin Configuration
40 39 38 37 36 35 34 33 32 31
vSADR_tri 1
30 NC
^vHIBW_BYPM_LOBW# 2
29 vOE3#
FB_DNC 3
28 DIF3#
FB_DNC# 4
VDDR1.5 5
9DBU0631
27 DIF3
26 VDDIO
CLK_IN 6
epad is GND
25 VDDA1.5
CLK_IN# 7
24 vOE2#
GNDDIG 8
23 DIF2#
SCLK_3.3 9
22 DIF2
SDATA_3.3 10
21 vOE1#
11 12 13 14 15 16 17 18 19 20
40-VFQFPN, 5mm x 5mm 0.4mm pin pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
Power Management Table
CKPWRGD_PD#
CLK_IN
SMBus
OEx bit
OEx# Pin
DIFx
True O/P Comp. O/P
0 X X X Low Low
1
Running
0
X Low Low
1
Running
1
0 Running Running
1
Running
1
1 Low Low
1. If Bypass mode is selected, the PLL will be off, and outputs will follow this table.
PLL
Off
On1
On1
On1
Power Connections
Pin Number
VDD
VDDIO
5
11
16,31
25
12,17,26,32,39
GND
41
8
41
41
Description
Input
receiver
analog
Digital Power
DIF outputs,
Logic
PLL Analog
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
6 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB
2
REVISION C 04/22/15









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9DBU0631 Даташит, Описание, Даташиты
9DBU0631 DATASHEET
Pin Descriptions
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1 vSADR_tri
2 ^vHIBW_BYPM_LOBW#
3 FB_DNC
4 FB_DNC#
5 VDDR1.5
6 CLK_IN
7 CLK_IN#
8 GNDDIG
9 SCLK_3.3
10 SDATA_3.3
11 VDDDIG1.5
12 VDDIO
13 vOE0#
14 DIF0
15 DIF0#
16 VDD1.5
17 VDDIO
18 DIF1
19 DIF1#
20 NC
21 vOE1#
22 DIF2
23 DIF2#
24 vOE2#
25 VDDA1.5
26 VDDIO
27 DIF3
28 DIF3#
29 vOE3#
30 NC
31 VDD1.5
32 VDDIO
33 DIF4
34 DIF4#
35 vOE4#
36 DIF5
37 DIF5#
38 vOE5#
39 VDDIO
40 ^CKPWRGD_PD#
41 ePAD
LATCHED Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
IN
LATCHED Trilevel input to select High BW, Bypass or Low BW mode.
IN See PLL Operating Mode Table for Details.
DNC
True clock of differential feedback. The feedback output and feedback input are connected
internally on this pin. Do not connect anything to this pin.
DNC
Complement clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
PWR
1.5V power for differential input clock (receiver). This VDD should be treated as an Analog
power rail and filtered appropriately.
IN True Input for differential reference clock.
IN Complementary Input for differential reference clock.
GND Ground pin for digital circuitry
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 1.5V digital power (dirty power)
PWR Power supply for differential outputs
IN Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR Power supply, nominally 1.5V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
N/A No Connection.
IN Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR 1.5V power for the PLL core.
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
N/A No Connection.
PWR Power supply, nominally 1.5V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
IN 1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high assertion. Low enters
IN Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal
pull-up resistor.
GND Connect paddle to ground.
REVISION C 04/22/15
3 6 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB










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