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PDF 9DB833 Data sheet ( Hoja de datos )
| Número de pieza | 9DB833 | |
| Descripción | EIGHT OUTPUT DIFFERENTIAL BUFFER | |
| Fabricantes | IDT | |
| Logotipo |  |
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DATASHEET
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
9DB833
General Description
The 9DB833 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB833 is driven by a differential
SRC output pair from an IDT 932S421 or 932SQ420 or
equivalent main clock generator.
Recommended Application
8 output PCIe Gen1,2,3 zero-delay/fanout buffer
Output Features
• 8 - 0.7V current-mode differential HCSL output pairs
• Supports zero delay buffer mode and fanout mode
• Selectable bandwidth
• 50-110 MHz operation in PLL mode
• 5-166 MHz operation in Bypass mode
Features/Benefits
• 3 Selectable SMBus Addresses; mulitple devices can
share the same SMBus Segment
• OE# pins; suitable for Express Card applications
• PLL or bypass mode; PLL can dejitter incoming clock
• Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible; tracks spreading input
clock for low EMI
• SMBus Interface; unused outputs can be disabled
• Supports undriven differential outputs in Power Down
mode for power management
Key Specifications
• Outputs cycle-cycle jitter <50ps
• Output to Output skew <50ps
• Phase jitter: PCIe Gen3 <1.0ps rm
Block Diagram
OE(7:0)#
8
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
M
U
X
STOP
LOGIC
8
DIF(7:0))
PD#
BYP#_LOBW_HIBW
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
LOCK
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
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9DB833
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9DB833
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DB833. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
PARAMETER
SYM BO L
CONDITIONS
3.3V Core Supply Voltage VDDA/R
3.3V Logic Supply Voltage
VDD
Input Low Voltage
V IL
Input High Voltage
VIH
Except for SMBus interface
Input High Voltage
VIHSM B
SMBus clock and data pins
Storage Temperature
Ts
Junction Temperature
Tj
Input ESD protection
ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
MIN
GND-0. 5
-65
20 00
TYP
MAX
4.6
4.6
VD D+ 0.5V
5. 5V
1 50
1 25
UNITS
V
V
V
V
V
°C
°C
V
N OTE S
1,2
1,2
1
1
1
1
1
1
Electrical Characteristics–Clock Input Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage - DIF_IN VIHDIF
Input Low Voltage - DIF_IN
Input Common Mode
Voltage - DIF_IN
VILDIF
VCOM
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
Common Mode Input Voltage
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
VSWING
dv/dt
Peak to Peak value
Measured differentially
Input Leakage Current
IIN
VIN = VDD , VIN = GND
Input Duty Cycle
dtin Measurement from differential waveform
Input Jitter - Cycle to Cycle JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
MIN
600
VSS - 300
300
300
1
-5
45
0
TYP
800
0
MAX
1150
UNITS NOTES
mV 1
300 mV 1
1000
1450
8
5
55
125
mV
mV
V/ns
uA
%
ps
1
1
1,2
1
1
1
Electrical Characteristics–Current Consumption
TA = TCOM or TI ND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYM BOL
CONDITIONS
Operating Supply Current IDD3.3 OP
All outputs active @100MHz, CL = Full load;
Powerdown Current
IDD3 .3PD
ID D3.3 PDZ
All diff pairs driven
All differential pairs tri-stated
1Guaranteed by design and characterization, not 100% tested in production.
MIN TYP MAX UNITS NOTES
170 200 mA 1
53 60 mA 1
3 6 mA 1
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
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9DB833
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9DB833
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
General SMBus Serial Interface Information
How to Write
• Controller (host) sends a start bit
• Controller (host) sends the write address*
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host)
T starT bit
IDT (Slave/Receiver)
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
O
OO
OO
O
Byte N + X - 1
ACK
P stoP bit
* Assuming SMB_ADR_tri is at mid-level
Read Address
DD(H)
Write Address
DC(H)
How to Read
• Controller (host) will send a start bit
• Controller (host) sends the write address*
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address*
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Controller (Host)
T starT bit
IDT (Slave/Receiver)
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
ACK
ACK
O
O
O
N Not acknowledge
P stoP bit
Data Byte Count=X
Beginning Byte N
O
O
O
Byte N + X - 1
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
11
9DB833
REV G 082515
11 Page | ||
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| PDF Descargar | [ Datasheet 9DB833.PDF ] | |
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