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9DB233 PDF даташит

Спецификация 9DB233 изготовлена ​​​​«IDT» и имеет функцию, называемую «Two Output Differential Buffer».

Детали детали

Номер произв 9DB233
Описание Two Output Differential Buffer
Производители IDT
логотип IDT логотип 

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9DB233 Даташит, Описание, Даташиты
DATASHEET
Two Output Differential Buffer for PCIe Gen3
9DB233
Recommended Application:
2 output PCIe Gen3 zero-delay/fanout buffer
General Description:
The 9DB233 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB233 is driven by a differential SRC
output pair from an IDT 932S421 or 932SQ420 or equivalent
main clock generator. It attenuates jitter on the input clock
and has a selectable PLL bandwidth to maximize
performance in systems with or without Spread-Spectrum
clocking. An SMBus interface allows control of the PLL
bandwidth and bypass options, while 2 clock request (OE#)
pins make the 9DB233 suitable for Express Card
applications.
Features/Benefits:
• OE# pins/Suitable for Express Card applications
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible/tracks spreading input
clock for low EMI
• SMBus Interface/unused outputs can be disabled
Output Features:
• 2 - 0.7V current mode differential output pairs (HCSL)
Key Specifications:
• Cycle-to-cycle jitter < 50 ps
• Output-to-output skew < 50 ps
• PCIe Gen3 phase jitter < 1.0ps RMS
Block Diagram
OE0#
OE1#
SRC_IN
SRC_IN#
PLL_BW
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
DIF_0
DIF_1
IREF
IDT® Two Output Differential Buffer for PCIe Gen3
1
1667C—04/20/11









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9DB233 Даташит, Описание, Даташиты
9DB233
Two Output Differential Buffer for PCIe Gen3
Pin Configuration
PLL_BW 1
SRC_IN 2
SRC_IN# 3
vOE0# 4
VDD 5
GND 6
DIF_0 7
DIF_0# 8
VDD 9
SMBDAT 10
20 VDDA
19 GNDA
18 IREF
17 vOE1#
16 VDD
15 GND
14 DIF_1
13 DIF_1#
12 VDD
11 SMBCLK
N ote: Pins preceeded by ' v ' have internal
120K ohm pull down resistors
Power Distribution Table
Pin Number
VDD
GND
5,9,12,16
6,15
96
20 19
20 19
Description
Differential Outputs
SMBUS
IREF
Analog VDD & GND for PLL core
Datasheet
IDT® Two Output Differential Buffer for PCIe Gen3
2
1667C—04/20/11









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9DB233 Даташит, Описание, Даташиты
9DB233
Two Output Differential Buffer for PCIe Gen3
Datasheet
Pin Description
PIN # PIN NAME PIN TYPE
DESC RIPTION
1 PLL_BW IN
2 SRC_IN IN
3 SRC_IN# IN
3.3V input for selecting PLL Band Width
0 = low, 1= high
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
4 vOE0# IN
Activ e low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
5 VDD
PWR
6 GND
PWR
7 DIF_0
OU T
8 DIF_0# OUT
9 VDD
PWR
10 SMBDAT I/O
11 SMBCLK IN
12 VDD
PWR
13 DIF_1# OUT
14 DIF_1
OU T
15 GND
PWR
16 VDD
PWR
17 vOE1# IN
18 IREF
OU T
19 GNDA
20 VDDA
PWR
PWR
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Data pin of SMBUS c ircuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Ground pin.
Power supply, nominal 3.3V
Activ e low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
Ground pin for the PLL core.
3.3V power for the PLL core.
Note:
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
IDT® Two Output Differential Buffer for PCIe Gen3
3
1667C—04/20/11










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Номер в каталогеОписаниеПроизводители
9DB233Two Output Differential BufferIDT
IDT

Номер в каталоге Описание Производители
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STMicroelectronics

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