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9DB1200C PDF даташит

Спецификация 9DB1200C изготовлена ​​​​«IDT» и имеет функцию, называемую «Twelve Output Differential Buffer».

Детали детали

Номер произв 9DB1200C
Описание Twelve Output Differential Buffer
Производители IDT
логотип IDT логотип 

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9DB1200C Даташит, Описание, Даташиты
DATASHEET
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI,
and FBDIMM
9DB1200C
Description
DB1200 Rev 2.0 Intel Yellow Cover Device
General Description
The ICS9DB1200 is an Intel DB1200 Differential Buffer
Specification device. This buffer provides 12 differential clocks
at frequencies ranging from 100MHz to 400 MHz. The
ICS9DB1200 is driven by a differential output from a CK410B+
or CK509B main clock generator.
Output Features
• 12 - 0.7V current-mode differential output pairs.
• Supports zero delay buffer mode and fanout mode.
• Bandwidth programming available.
• 100-400 MHz operation in PLL mode
• 33-400 MHz operation in Bypass mode
Features/Benefits
• 3 selectable SMBus addresses for easy system expansion
• Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
• Supports undriven differential outputs in Power Down Mode
for power management.
Key Specifications
• Output cycle-cycle jitter < 50ps.
• Output to output skew: 50ps
• Phase jitter: PCIe Gen2 < 3.1ps rms
• Phase jitter: QPI < 0.5ps rms
• 64-pin TSSOP Package
• Available in RoHS compliant packaging
Functional Block Diagram
12
OE_(11:0)#
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
FS(2:0)
HIGH_BW#
BYPASS#/PLL
VTTPWRGD#/PD
ADR_SEL
SMBDAT
SMBCLK
CONTROL
LOGIC
M
U
X
12
DIF(11:0))
IREF
IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
1
1414F—06/30/10









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9DB1200C Даташит, Описание, Даташиты
9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
Pin Configuration
VDD 1
64 VDDA
DIF_IN 2
63 AGND
DIF_IN# 3
62 IREF
GND 4
OE0# 5
DIF_0 6
DIF_0# 7
VDD 8
GND 9
61 FS0
60 OE11#
59 DIF_11
58 DIF_11#
57 VDD
56 GND
OE1# 10
55 OE10#
DIF_1 11
54 DIF_10
DIF_1# 12
53 DIF_10#
OE2# 13
52 OE9#
DIF_2 14
51 DIF_9
DIF_2# 15
50 DIF_9#
GND 16
VDD 17
OE3# 18
DIF_3 19
DIF_3# 20
OE4# 21
49 GND
48 VDD
47 OE8#
46 DIF_8
45 DIF_8#
44 OE7#
DIF_4 22
43 DIF_7
DIF_4# 23
42 DIF_7#
VDD 24
41 VDD
GND 25
40 GND
OE5# 26
39 OE6#
DIF_5 27
38 DIF_6
DIF_5# 28
**ADR_SEL 29
HIGH_BW# 30
FS2 31
SMBCLK 32
37 DIF_6#
36 VTTPWRGD#/PD
35 BYPASS#/PLL
34 FS1
33 SMBDAT
64-TSSOP
** Indicates 120K ohm Pulldown
Frequency Select Table
FSL2
B0b2
FSL1
B0b1
FSL0
B0b0
Input
MHz
DIF_x;
MHz
0 0 0 266.66 266.66
0 0 1 133.33 133.33
0 1 0 200.00 200.00
0 1 1 166.66 166.66
1 0 0 333.33 333.33
1 0 1 100.00 100.00
1 1 0 400.00 400.00
1 1 1 Hi-Z Hi-Z
1. FSL(2:0) are 3.3V tolerant low-threshold inputs.
Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
SMBus Address Selection (Pin 29)
ADR_SEL
Voltage SMBus Adr (Wr/Rd)
Low <0.8V
DC/DD
Mid 1.2<Vin<1.8V
D6/D7
High
Vin > 2.0V
D4/D5
Power Groups
Pin Number
VDD
GND
Description
1 4 DIF_IN/DIF_IN#
8, 17, 24, 41, 9, 16, 25, 40,
48, 57
49, 56
DIF(11:0)
N/A 63
IREF
64 63 Analog VDD & GND
for PLL core
Note: Please treat pin 1 as an analog VDD.
IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
1414F—06/30/10
2









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9DB1200C Даташит, Описание, Даташиты
9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
Pin Description
PIN #
1
2
3
4
PIN NAME
VDD
DIF_IN
DIF_IN#
GND
5 OE0#
6 DIF_0
7 DIF_0#
8 VDD
9 GND
10 OE1#
11 DIF_1
12 DIF_1#
13 OE2#
14 DIF_2
15 DIF_2#
16 GND
17 VDD
18 OE3#
19 DIF_3
20 DIF_3#
21 OE4#
22 DIF_4
23 DIF_4#
24 VDD
25 GND
26 OE5#
27 DIF_5
28 DIF_5#
29 **ADR_SEL
30 HIGH_BW#
31 FS2
32 SMBCLK
TYPE
PWR
IN
IN
PWR
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
IN
IN
IN
DESCRIPTION
Power supply, nominal 3.3V
0.7 V Differential TRUE input
0.7 V Differential Complementary Input
Ground pin.
Active low input for enabling DIF pair 0.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
Active low input for enabling DIF pair 1.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 2.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
Active low input for enabling DIF pair 3.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 4
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
Active low input for enabling DIF pair 5.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
This tri-level input selects one of 3 SMBus addresses. See the SMBus
Address Select Table for the addresses.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Frequency select pin.
Clock pin of SMBUS circuitry, 5V tolerant
IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
3
1414F—06/30/10










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Номер в каталогеОписаниеПроизводители
9DB1200CTwelve Output Differential BufferIDT
IDT

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