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PDF 49LF004B Data sheet ( Hoja de datos )
| Número de pieza | 49LF004B | |
| Descripción | SST49LF004B | |
| Fabricantes | Silicon Storage Technology | |
| Logotipo |  |
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4 Mbit LPC Firmware Flash
SST49LF004B
FEATURES:
SST49LF004B4Mb LPC Firmware memory
Data Sheet
• SST49LF004B: 512K x8 (4 Mbit)
• Conforms to Intel LPC Interface Specification 1.1
– Supports Single-Byte LPC Memory and
Firmware Memory Cycle Types
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 64 KByte overlay blocks
– Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
• Two Operational Modes
– Low Pin Count (LPC) interface mode for
in-system operation
– Parallel Programming (PP) mode for fast
production programming
• LPC Interface Mode
– 5-signal LPC bus interface supporting byte Read
and Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write
protect for entire chip and/or top Boot Block
– Block Locking Registers for individual block
write-lock and lock-down protection
– JEDEC Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Write
detection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
• Parallel Programming (PP) Mode
– 11-pin multiplexed address and 8-pin data
I/O interface
– Supports fast programming in-system on
programmer equipment
• CMOS and PCI I/O Compatibility
• Packages Available
– 32-lead PLCC
– 40-lead TSOP (10mm x 20mm)
PRODUCT DESCRIPTION
The SST49LF004B flash memory device is designed to
interface with host controllers (chipsets) that support a low-
pin-count (LPC) interface for BIOS applications. The
SST49LF004B device complies with Intel’s LPC Interface
Specification 1.1, supporting single-byte Firmware Memory
and LPC Memory cycle types.
The SST49LF004B is backward compatible to the
SST49LF00xA Firmware Hub and the SST49LF0x0A LPC
Flash. In this document, FWH mode in the SST49LF00xA
specification is referenced as the Firmware Memory Read/
Write cycle and LPC mode in the SST49LF0x0A specifica-
tion is referenced as the LPC Memory Read/Write cycle.
Two interface modes are supported by the SST49LF004B:
LPC mode (Firmware Memory and LPC Memory cycle
types) for in-system operations and Parallel Programming
(PP) mode to interface with programming equipment.
The SST49LF004B flash memory device is manufactured
with SST’s proprietary, high-performance SuperFlash tech-
nology. The split-gate cell design and thick-oxide tunneling
injector attain greater reliability and manufacturability com-
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
1
pared with alternative approaches. The SST49LF004B
device significantly improves performance and reliability,
while lowering power consumption. The SST49LF004B
device writes (Program or Erase) with a single 3.0-3.6V
power supply.
The SST49LF004B provides a maximum Byte-Program
time of 20 µsec. The entire memory can be erased and
programmed byte-by-byte in 8 seconds when using status
detection features such as Toggle Bit or Data# Polling to
indicate the completion of Program operation. To protect
against inadvertent writes, the SST49LF004B device has
on-chip hardware and software write protection schemes. It
is offered with a typical endurance of 100,000 cycles. Data
retention is rated at greater than 100 years.
The SST49LF004B uses less energy during Erase and
Program than alternative flash memory technologies. The
total energy consumed is a function of the applied voltage,
current and time of application. Since for any given voltage
range the SuperFlash technology uses less current to pro-
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
Intel is a registered trademark of Intel Corporation.
These specifications are subject to change without notice.
1 page  
4 Mbit LPC Firmware Flash
SST49LF004B
LIST OF TABLES
Data Sheet
TABLE 1: Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TABLE 2: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TABLE 3: Firmware and LPC Memory Cycles START Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
TABLE 4: Firmware Memory Read Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
TABLE 5: Firmware Memory Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TABLE 6: LPC Memory Read Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TABLE 7: LPC Memory Write Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TABLE 8: Firmware Memory Multiple Device Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TABLE 9: LPC Memory Multiple Device Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TABLE 10: Block Locking Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TABLE 11: Block Locking Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TABLE 12: Operation Modes Selection (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TABLE 13: Software Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TABLE 14: DC Operating Characteristics (All Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TABLE 15: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TABLE 16: Pin Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TABLE 17: Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TABLE 18: Clock Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TABLE 19: Read/Write Cycle Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TABLE 20: AC Input/Output Specifications (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TABLE 21: Interface Measurement Condition Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TABLE 22: Reset Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TABLE 23: Reset Timing Parameters (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TABLE 24: Read Cycle Timing Parameters (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TABLE 25: Program/Erase Cycle Timing Parameters (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TABLE 26: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
©2003 Silicon Storage Technology, Inc.
5
S71232-02-000
12/03
5 Page 
4 Mbit LPC Firmware Flash
SST49LF004B
MODE SELECTION
The SST49LF004B flash memory device operates in two
distinct interface modes: the LPC mode and the Parallel
Programming (PP) mode. In LPC mode, communication
between the Host and the SST49LF004B occurs via the 4-
bit I/O communication signals, LAD[3:0], and LFRAME#. In
PP mode, the device is controlled via the 11 addresses,
A10-A0, and 8 I/O, DQ7-DQ0, signals. The address inputs
are multiplexed in row and column selected by control sig-
nal R/C# pin. The row addresses are mapped to the lower
internal addresses (A10-0), and the column addresses are
mapped to the higher internal addresses (A18-11). See Fig-
ure 3, Device Memory Map, for address assignments.
LPC MODE
Data Sheet
Device Operation
The LPC mode uses a 5-signal communication interface
consisting of one control line, LFRAME#, which is driven by
the host to start or abort a bus cycle, and a 4-bit data bus,
LAD[3:0], which is used to communicate cycle type, cycle
direction, ID selection, address, data and sync fields. The
device enters standby mode when LFRAME# is high and
no internal operation is in progress.
The SST49LF004B supports both single-byte Firmware
Memory Read/Write cycles and single-byte LPC Memory
Read/Write cycles as defined in Intel’s Low-Pin-Count
Interface Specification, Revision 1.1. The host drives
LFRAME# low for one or more clock cycles to initiate an
LPC cycle. The last latched value of LAD[3:0] before
LFRAME# is the START value. The START value deter-
mines whether the SST49LF004B will respond to a Firm-
ware Memory Read/Write cycle or a LPC Memory Read/
Write cycle as defined in Table 3.
TABLE 3: FIRMWARE AND LPC MEMORY CYCLES
START FIELD DEFINITION
START
Value Definition
0000
Start of an LPC memory cycle. The direction
(Read or Write) is determined by the second field
of the LPC cycle.
1101 Start of a Firmware Memory Read cycle
1110 Start of a Firmware Memory Write cycle
T3.0 1232
See following sections for details of Firmware Memory and
LPC Memory cycle types. JEDEC standard SDP (Soft-
ware Data Protection) Program and Erase command
sequences are used to initiate Firmware and LPC Memory
Program and Erase operations. See Table 12 for a listing
of Program and Erase commands. Chip-Erase is only
available in PP mode.
©2003 Silicon Storage Technology, Inc.
11
S71232-02-000
12/03
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 49LF004B.PDF ] | |
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