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9FGV0831 PDF даташит

Спецификация 9FGV0831 изготовлена ​​​​«IDT» и имеет функцию, называемую «8-O/P 1.8V PCIe Gen 1/2/3 Clock Generator».

Детали детали

Номер произв 9FGV0831
Описание 8-O/P 1.8V PCIe Gen 1/2/3 Clock Generator
Производители IDT
логотип IDT логотип 

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9FGV0831 Даташит, Описание, Даташиты
8-O/P 1.8V PCIe Gen 1/2/3 Clock Generator
9FGV0831
DATASHEET
Description
The 9FGV0831 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power PCIe clock family. The device has 8 output
enables for clock management, 2 different spread spectrum
levels in addition to spread off and 2 selectable SMBus
addresses.
Recommended Application
1.8V PCIe Gen1/2/3 clock generator
Output Features
8 - 100MHz Low-Power (LP) HCSL DIF pair
1 - 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 1.5ps RMS
Block Diagram
Features/Benefits
LP-HCSL outputs; save 16 resistors compared to standard
PCIe devices
62mW typical power consumption; reduced thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05 and 1.8V; maximum power savings
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Space saving 48-pin 6x6 mm VFQFPN; minimal board
space
vOE(7:0)#
XIN/CLKIN_25
X2
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.8
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9FGV0831 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.









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9FGV0831 Даташит, Описание, Даташиты
9FGV0831 DATASHEET
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
vSS_EN_tri 1
36 DIF5#
GNDXTAL 2
35 DIF5
X1_25 3
34 vOE4#
X2 4
33 DIF4#
VDDXTAL1.8 5
32 DIF4
VDDREF1.8 6
vSADR/REF1.8 7
9FGV0831
31 VDDIO
30 VDDA1.8
GNDREF 8
29 GNDA
GNDDIG 9
28 vOE3#
SCLK_3.3 10
27 DIF3#
SDATA_3.3 11
26 DIF3
VDDDIG1.8 12
25 vOE2#
13 14 15 16 17 18 19 20 21 22 23 24
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
vv prefix indicates internal 60KOhm pull down resistor
v prefix indicates internal 120KOhm pull down resistor
^ prefix indicates internal 120KOhm pull up resistor
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
+ Read/Write Bit
x
x
Power Management Table
CKPWRGD_PD#
SMBus
OE bit
OEx#
DIFx
True O/P
Comp. O/P
REF
0 X X Low Low Hi-Z1
1
1
0
Running
Running Running
1 0 1 Low Low Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is Low.
Power Connections
Pin Number
VDD
5
6
12
20,38
30
VDDIO
13,21,31,39,
47
GND
2
8
9
22,29,40
29
Description
XTAL OSC
REF Power
Digital (dirty)
Power
DIF outputs
PLL Analog
8-O/P 1.8V PCIE GEN 1/2/3 CLOCK GENERATOR
2
OCTOBER 18, 2016









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9FGV0831 Даташит, Описание, Даташиты
9FGV0831 DATASHEET
Pin Descriptions
PIN # PIN NAME
1 vSS_EN_tri
2 GNDXTAL
3 X1_25
4 X2
5 VDDXTAL1.8
6 VDDREF1.8
7 vSADR/REF1.8
8 GNDREF
9 GNDDIG
10 SCLK_3.3
11 SDATA_3.3
12 VDDDIG1.8
13 VDDIO
14 vOE0#
15 DIF0
16 DIF0#
17 vOE1#
18 DIF1
19 DIF1#
20 VDD1.8
21 VDDIO
22 GND
23 DIF2
24 DIF2#
25 vOE2#
26 DIF3
27 DIF3#
28 vOE3#
29 GNDA
30 VDDA1.8
31 VDDIO
32 DIF4
33 DIF4#
34 vOE4#
35 DIF5
36 DIF5#
37 vOE5#
38 VDD1.8
39 VDDIO
TYPE
DESCRIPTION
LATCHED Latched select input to select spread spectrum amount at initial power up :
IN 1 = -0.5% spread, M = -0.25%, 0 = Spread Off
GND GND for XTAL
IN Crystal input, Nominally 25.00MHz.
OUT Crystal output.
PWR Power supply for XTAL, nominal 1.8V
PWR VDD for REF output. nominal 1.8V.
LATCHED Latch to select SMBus Address/1.8V LVCMOS copy of X1/REFIN pin
I/O
GND Ground pin for the REF outputs.
GND Ground pin for digital circuitry
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 1.8V digital power (dirty power)
PWR Power supply for differential outputs
IN Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR Power supply, nominal 1.8V
PWR Power supply for differential outputs
GND Ground pin.
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
GND Ground pin for the PLL core.
PWR 1.8V power for the PLL core.
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply, nominal 1.8V
PWR Power supply for differential outputs
OCTOBER 18, 2016
3 8-O/P 1.8V PCIE GEN 1/2/3 CLOCK GENERATOR










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Номер в каталогеОписаниеПроизводители
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