8SLVP1208 Datasheet PDF - IDT
| Part Number | 8SLVP1208 | |
| Description | LVPECL Output Fanout Buffer | |
| Manufacturers | IDT | |
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Low Phase Noise, 1-to-8, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP1208
DATA SHEET
General Description
The 8SLVP1208 is a high-performance differential LVPECL fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVP1208 is
characterized to operate from a 3.3V and 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVP1208 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
selectable differential inputs and eight low skew outputs are available.
The integrated bias voltage generators enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
• Eight low skew, low additive jitter LVPECL output pairs
• Two selectable, differential clock input pairs
• Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
• Maximum input clock frequency: 2GHz
• LVCMOS interface levels for the control input (input select)
• Output skew: 28ps (typical)
• Propagation delay: 410ps (maximum)
• Low additive phase jitter, RMS: 54.1fs (maximum)
(fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz)
• Full 3.3V and 2.5V supply voltage
• Maximum device current consumption (IEE): 141mA
• Available in lead-free (RoHS 6), 28-Lead VFQFN package
• -40°C to 85°C ambient operating temperature
• Differential PCLK0, nPCLK0 and PCLK1, nPCLK1 pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input to Accept Single-Ended Levels
(Figure 1A and Figure 1B)
Block Diagram
VCC
PCLK0
nPCLK0
Pulldown
Pullup/Pulldown
VCC
PCLK1
nPCLK1
Pulldown
Pullup/Pulldown
0 fREF
1
SEL Pulldown
VREF
Voltage
Reference
8SLVP1208 REVISION 1 08/28/14
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6 8SLVP1208
nQ6 28-Lead LFCSP
Q7 5mm x 5mm x 0.75mm package body
nQ7 NB Package
Top View
1 ©2014 Integrated Device Technology, Inc.
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8SLVP1208 DATA SHEET
AC Electrical Characteristics
Table 5A. AC Electrical Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C1
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
Input
PCLK[0:1],
fREF Frequency nPCLK[0:1]
2 GHz
V/t
Input
PCLK[0:1],
Edge Rate nPCLK[0:1]
1.5 V/ns
tPD
tsk(o)
tsk(i)
Propagation Delay2
Output Skew3, 4
Input Skew4
PCLK[0:1], nPCLK[0:1] to any Qx, nQx
160 287 410 ps
for VPP,IN = 0.1V or 0.3V
28 64 ps
12 65 ps
tsk(p)
tsk(pp)
Pulse Skew
Part-to-Part Skew4, 5
fREF = 100MHz
29 70 ps
55 140 ps
tR / tF
MUXISOLATION
VPP
Output Rise/ Fall Time
Mux Isolation6
Peak-to-Peak
Input Voltage7, 8
20% to 80%
f < 1.5GHz
f > 1.5GHz
29 104 200 ps
76 dB
0.1 1.5 V
0.2 1.5 V
VCMR
Common Mode
Input Voltage7, 8, 9
1.0
VCC – 0.6
V
Vo (pp)
Output Voltage Swing,
Peak-to-Peak
VCC = 3.3V, fREF 2GHz
VCC = 2.5V, fREF 2GHz
0.5 0.83 1.10 V
0.5 0.82 1.05 V
VDIFF_OUT
Differential Output Voltage
Swing, Peak to Peak
VCC = 3.3V, fREF 2GHz
VCC = 2.5V, fREF 2GHz
1.0 1.67 2.20 V
1.0 1.63 2.10 V
NOTE 1: NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 2: Measured from the differential input crossing point to the differential output crossing point.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 6: Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section.
NOTE 7: VIL should not be less than -0.3V. VIH should not be higher than VCC.
NOTE 8: For single-ended LVCMOS input applications, please refer to the Applications Information, Wiring the Differential Input to Accept Sin-
gle-Ended Levels, Figure 1A and Figure 1B.
NOTE 9: Common mode input voltage is defined as the crosspoint.
REVISION 1 08/28/14
5 LOW PHASE NOISE, 1-TO-8, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
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| Information | Total 23 Pages | |
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