6810 PDF даташит
Спецификация 6810 изготовлена «Allegro» и имеет функцию, называемую «LATCHED SOURCE DRIVER». |
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Детали детали
Номер произв | 6810 |
Описание | LATCHED SOURCE DRIVER |
Производители | Allegro |
логотип |
8 Pages
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6810
A6810xA
OUT8 1
OUT7 2
OUT6 3
CLOCK 4 CLK
GROUND 5
LOGIC
SUPPLY
6 VDD
STROBE 7 ST
OUT 5 8
OUT4 9
18 OUT 9
LATCHES
REGISTER
REGISTER
LATCHES
17 OUT 10
16
SERIAL
DATA OUT
VBB 15
LOAD
SUPPLY
14 SERIAL
DATA IN
BLNK 13 BLANKING
12 OUT1
11 OUT 2
10 OUT 3
Dwg. PP-029
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD ................... 7.0 V
Driver Supply Voltage, VBB ................... 60 V
Continuous Output Current Range,
IOUT ......................... -40 mA to +15 mA
Input Voltage Range,
VIN ....................... -0.3 V to VDD + 0.3 V
Package Power Dissipation,
PD ........................................ See Graph
Operating Temperature Range, TA
(Suffix ‘E–’) .................. -40°C to +85°C
(Suffix ‘S–’) .................. -20°C to +85°C
Storage Temperature Range,
TS ............................... -55°C to +125°C
Caution: These CMOS devices have input
static protection (Class 2) but are still
susceptible to damage if exposed to
extremely high static electrical charges.
DABiC-IV, 10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
The A6810– devices combine 10-bit CMOS shift registers, accom-
panying data latches and control circuitry with bipolar sourcing outputs
and pnp active pull downs. Designed primarily to drive vacuum-
fluorescent displays, the 60 V and -40 mA output ratings also allow
these devices to be used in many other peripheral power driver applica-
tions. The A6810– feature an increased data input rate (compared with
the older UCN/UCQ5810-F) and a controlled output slew rate.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply,
serial-data input rates of at least 10 MHz .
A CMOS serial data output permits cascade connections in applica-
tions requiring additional drive lines. Similar devices are available as
the A6812– (20 bits) and A6818– (32 bits).
The A6810– output source drivers are npn Darlingtons, capable of
sourcing up to 40 mA. The controlled output slew rate reduces electro-
magnetic noise, which is an important consideration in systems that
include telecommunications and/or microprocessors and to meet
government emissions regulations. For inter-digit blanking, all output
drivers can be disabled and all sink drivers turned on with a BLANK-
ING input high. The pnp active pull-downs will sink at least
2.5 mA.
The A6810– are available in two temperature ranges for optimum
performance in commercial (suffix S-) or industrial (suffix E-) applica-
tions. They are provided in two package styles for through-hole DIP
(suffix -A) or minimum-area surface-mount SOIC (suffix -LW).
Copper lead frames, low logic-power dissipation, and low output-
saturation voltages allow all devices to source 25 mA from all outputs
continuously over the maximum operating temperature range.
FEATURES
s Controlled Output Slew Rate
s High-Speed Data Storage
s 60 V Minimum
Output Breakdown
s High Data Input Rate
s PNP Active Pull-Downs
s Improved Replacements
for TL4810–, UCN5810–,
and UCQ5810–
s Low Output-Saturation Voltages
s Low-Power CMOS Logic
and Latches
Complete part number includes a suffix to identify operating
temperature range (E- or S-) and package type (-A or -LW). Always
order by complete part number, e.g., A6810SLW .
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6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
TYPICAL OUTPUT DRIVER
V BB
OUTN
Dwg. EP-021-19
A6810xLW
OUT 8 1
OUT7 2
OUT 6 3
CLOCK 4 CLK
GROUND 5
LOGIC SUPPLY 6 VDD
STROBE 7 ST
OUT 5 8
OUT 4 9
NO 10 NC
CONNECTION
20 OUT9
LATCHES
REGISTER
REGISTER
LATCHES
19 OUT10
18 SERIAL
DATA OUT
VBB 17 LOAD SUPPLY
16
BLNK 15
SERIAL
DATA IN
BLANKING
14 OUT1
13 OUT2
12 OUT3
NC 11
NO
CONNECTION
Dwg. PP-029-2
TYPICAL INPUT CIRCUIT
VDD
IN
2.5
Dwg. EP-010-5
2.0
SUFFIX 'A', RθJA = 65°C/W
1.5
1.0
SUFFIX 'LW', RθJA = 90°C/W
0.5
0
25
50 75 100 125
AMBIENT TEMPERATURE IN °C
150
Dwg. GS-009-1B
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1998, 2003 Allegro MicroSystems, Inc.
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6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
GROUND
FUNCTIONAL BLOCK DIAGRAM
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
V DD
LOGIC
SUPPLY
SERIAL
DATA OUT
OUT 1 OUT 2 OUT 3
MOS
BIPOLAR
VBB
LOAD
SUPPLY
OUT N
Dwg. FP-013-1
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
Serial
Data Strobe
Output Input
Latch Contents
Output Contents
I1 I2 I3 ... IN-1 IN Blanklng I1 I2 I3 ... IN-1 IN
H H R1 R2 ... RN-2 RN-1 RN-1
L L R1 R2 ... RN-2 RN-1 RN-1
X
R1 R2 R3 ... RN-1 RN
RN
X X X ... X X
X
L R1 R2 R3 ... RN-1 RN
P1 P2 P3 ... PN-1 PN
PN
H P1 P2 P3 ... PN-1 PN
X X X ... X X
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
L
H
P1 P2 P3 ... PN-1 PN
L L L ... L L
www.allegromicro.com
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