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PDF MC54HC563A Data sheet ( Hoja de datos )
| Número de pieza | MC54HC563A | |
| Descripción | Octal 3-State Inverting Transparent Latch | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC54HC563A (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Inverting
Transparent Latch
High–Performance Silicon–Gate CMOS
The MC54/74HC563A is identical in pinout to the LS563. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device is identical in function to the HC533A but has the Data Inputs
on the opposite side of the package from the outputs to facilitate PC board
layout.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. The data appears at the outputs
in inverted form. When Latch Enable goes low, data meeting the setup and
hold time becomes latched.
The Output Enable input does not affect the state of the latches, but when
Output Enable is high, all device outputs are forced to the high–impedance
state. Thus, data may be latched even when the outputs are not enabled.
The HC573A is the noninverting version of this function.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 202 FETs or 50.5 Equivalent Gates
LOGIC DIAGRAM
D0 2
D1 3
D2 4
DATA D3 5
INPUTS D4 6
D5 7
D6 8
D7 9
LATCH
ENABLE
OUTPUT
ENABLE
11
1
19
Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
INVERTING
OUTPUTS
PIN 20 = VCC
PIN 10 = GND
MC54/74HC563A
20
1
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC54HCXXXAJ Ceramic
MC74HCXXXAN Plastic
MC74HCXXXADW SOIC
PIN ASSIGNMENT
OUTPUT
ENABLE
1
D0 2
20 VCC
19 Q0
D1 3
18 Q1
D2 4
17 Q2
D3 5
16 Q3
D4 6
15 Q4
D5 7
14 Q5
D6 8
13 Q6
D7 9
GND 10
12 Q7
11 LATCH
ENABLE
FUNCTION TABLE
Inputs
Output
Output Latch
Enable Enable D
Q
L HH L
L HL H
L L X No Change
H XX Z
X = don’t care
Z = high impedance
8/96
© Motorola, Inc. 1996
1
REV 0
1 page  
MC54/74HC563A
SWITCHING WAVEFORMS
tr
INPUT D
tPHL
Q
90%
50%
10%
90%
50%
10%
tTHL
Figure 1.
tf
VCC
GND
tPLH
tTLH
LATCH
ENABLE
Q
tw
50%
tPLH tPHL
50%
Figure 2.
OUTPUT ENABLE
Q
Q
50%
tPZL tPLZ
50%
tPZH tPHZ
50%
Figure 3.
VCC
GND
HIGH
IMPEDANCE
10% VOL
90% VOH
HIGH
IMPEDANCE
INPUT D
LATCH
ENABLE
VALID
50%
tsu
th
50%
Figure 4.
VCC
GND
VCC
GND
VCC
GND
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
TEST CIRCUITS
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
* Includes all probe and jig capacitance
Figure 5.
* Includes all probe and jig capacitance
Figure 6.
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC54HC563A.PDF ] | |
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