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PDF MC54HC164A Data sheet ( Hoja de datos )
| Número de pieza | MC54HC164A | |
| Descripción | 8-Bit Serial Input / Parallel Output Shift Register | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8-Bit Serial-Input/
Parallel-Output Shift Register
High–Performance Silicon–Gate CMOS
The MC54/74HC164A is identical in pinout to the LS164. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The MC54/74HC164A is an 8–bit, serial–input to parallel–output shift
register. Two serial data inputs, A1 and A2, are provided so that one input
may be used as a data enable. Data is entered on each rising edge of the
clock. The active–low asynchronous Reset overrides the Clock and Serial
Data inputs.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 244 FETs or 61 Equivalent Gates
LOGIC DIAGRAM
SERIAL A1 1
DATA
2
INPUTS A2
DATA
8
CLOCK
3
QA
4
QB
5
QC
6
QD
10
QE
11 QF
12 QG
13
QH
PARALLEL
DATA
OUTPUTS
9
RESET
PIN 14 = VCC
PIN 7 = GND
FUNCTION TABLE
Inputs
Outputs
Reset Clock A1 A2 QA QB … QH
L X X X L L …L
H
XX
No Change
H H D D QAn … QGn
H D H D QAn … QGn
D = data input
QAn – QGn = data shifted from the preceding
stage on a rising edge at the clock input.
MC54/74HC164A
14
1
14
1
14
1
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
1
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
PIN ASSIGNMENT
A1 1
A2 2
QA 3
QB 4
QC 5
QD 6
GND 7
14 VCC
13 QH
12 QG
11 QF
10 QE
9 RESET
8 CLOCK
3/96
© Motorola, Inc. 1996
3–1 REV 0
1 page  
MC54/74HC164A
PIN DESCRIPTIONS
INPUTS
A1, A2 (Pins 1, 2)
Serial Data Inputs. Data at these inputs determine the data
to be entered into the first stage of the shift register. For a
high level to be entered into the shift register, both A1 and A2
inputs must be high, thereby allowing one input to be used as
a data–enable input. When only one serial input is used, the
other must be connected to VCC.
Clock (Pin 8)
Shift Register Clock. A positive–going transition on this pin
shifts the data at each stage to the next stage. The shift
register is completely static, allowing clock rates down to DC
in a continuous or intermittent mode.
OUTPUTS
QA – QH (Pins 3, 4, 5, 6, 10, 11, 12, 13)
Parallel Shift Register Outputs. The shifted data is pres-
ented at these outputs in true, or noninverted, form.
CONTROL INPUT
Reset (Pin 9)
Active–Low, Asynchronous Reset Input. A low voltage ap-
plied to this input resets all internal flip–flops and sets Out-
puts QA – QH to the low level state.
CLOCK
Q
tr
90%
50%
10%
tw
tf
90%
50%
10%
1/fmax
tPLH tPHL
tTLH tTHL
Figure 1.
SWITCHING WAVEFORMS
VCC RESET
GND
tPHL
Q
CLOCK
tw
50%
50%
trec
50%
Figure 2.
VCC
GND
VCC
GND
A1 OR A2
CLOCK
VALID
50%
tsu th
50%
Figure 3.
VCC
GND
VCC
GND
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 4. Test Circuit
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5
MOTOROLA
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MC54HC164A.PDF ] | |
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