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PDF 8T73S1802 Data sheet ( Hoja de datos )
| Número de pieza | 8T73S1802 | |
| Descripción | 1:2 Clock Fanout Buffer and Frequency Divider | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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1:2 Clock Fanout Buffer and Frequency Divider 8T73S1802
DATA SHEET
General Description
Features
The 8T73S1802 is a fully integrated clock fanout buffer and frequency
divider. The input signal is frequency-divided and then fanned out to
one differential LVPECL and one LVCMOS output. Each of the
outputs can select its individual divider value from the range of ÷1,
÷2, ÷4 and ÷8. Three control inputs EN, SEL0 and SEL1 (3-level
logic) are available to select the frequency dividers and the output
enable/disable state. The single-ended LVCMOS output is
phase-delayed by 650ps to minimize coupling of LVCMOS switching
into the differential output during its signal transition.
The 8T73S1802 is optimized to deliver very low phase noise clocks.
The VBB output generates a common-mode voltage reference for the
differential clock input so that connecting the VBB pin to an unused
input (nCLK) enables to use of single-ended input signals. The
extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
The 8T73S1802 can be used with a 3.3V or a 2.5V power supply. The
device is a member of the high-performance clock family from IDT.
• High-performance fanout buffer clock and fanout buffer
• Input clock signal is distributed to one LVPECL and one LVCMOS
output
• Configurable output dividers for both LVPECL and LVCMOS
outputs
• Supports clock frequencies up to 1000MHz (LVPECL) and up to
200MHz (LVCMOS)
• Flexible differential input supports LVPECL, LVDS and CML
• VBB generator output supports single-ended input signal
applications
• Optimized for low phase noise
• 650ps delay between LVCMOS and LVPECL minimizes coupling
between outputs
• Supply voltage: 3.3V or 2.5V
• -40°C to 85°C ambient operating temperature
• 16 VFQFN package (3mm x 3mm)
8T73S1802 REVISION 1 08/31/15
1 ©2015 Integrated Device Technology, Inc.
1 page  
8T73S1802 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, VCC
Inputs, VI
Outputs, VO (LVCMOS)
Outputs, IO (LVPECL)
Continuous Current
Surge Current
Maximum Junction Temperature, TJ_MAX
Storage Temperature, TSTG
ESD - Human Body Model1
ESD - Charged Device Model
Rating
3.6V
-0.5V to VCC + 0.5V
-0.5V to VCCO_QB + 0.5V
10mA
15mA
125°C
-65°C to 150°C
2000V
1500V
NOTE 1. According to JEDEC/JESD 22-A114/22-C101.
Electrical Characteristics
Table 4A. 3.3V Power Supply Characteristics, VCC = VCCO_QA = VCCO_QB = 3.0V to 3.465V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VCC
VCCO_QA,
VCCO_QB
Power Supply Voltage
Output Supply Voltage
ICC Power Supply Current1
ICCZ
Power Supply Current1
IEE Power Supply Current
All outputs enabled and terminated with
50 to VCC – 2V on LVPECL outputs and
10pF on LVCMOS output;
f = 800MHz for LVPECL outputs and
200MHz for LVCMOS, VCC = 3.3V
Outputs enabled, no load;
f = 800MHz for LVPECL outputs and
200MHz for LVCMOS, VCC = 3.465V
Outputs Disabled, EN = 0,
fIN = 0Hz, VCC = 3.465V
All outputs enabled and terminated with
50 to VCC – 2V on LVPECL outputs and
10pF on LVCMOS output;
f = 800MHz for LVPECL outputs and
200MHz for LVCMOS
3.0
3.0
3.3 3.465
3.3 3.465
120
104
8.2
92 109
NOTE 1. ICC includes output current.
Units
V
V
mA
mA
mA
mA
REVISION 1 08/31/15
5 1:2 CLOCK FANOUT BUFFER AND FREQUENCY DIVIDER
5 Page 
8T73S1802 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 250MHz
12kHz to 20MHz = 79fs (typical)
REVISION 1 08/31/15
Offset from Carrier Frequency (Hz)
11 1:2 CLOCK FANOUT BUFFER AND FREQUENCY DIVIDER
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet 8T73S1802.PDF ] | |
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