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AD5346 PDF даташит

Спецификация AD5346 изготовлена ​​​​«Analog Devices» и имеет функцию, называемую «Parallel Interface Octal Voltage Output 8-/10-/12-Bit DACs».

Детали детали

Номер произв AD5346
Описание Parallel Interface Octal Voltage Output 8-/10-/12-Bit DACs
Производители Analog Devices
логотип Analog Devices логотип 

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AD5346 Даташит, Описание, Даташиты
Data Sheet
2.5 V to 5.5 V, Parallel Interface
Octal Voltage Output 8-/10-/12-Bit DACs
AD5346/AD5347/AD5348
FEATURES
GENERAL DESCRIPTION
AD5346: octal 8-bit DAC
The AD5346/AD5347/AD53481 are octal 8-, 10-, and 12-bit
AD5347: octal 10-bit DAC
DACs, operating from a 2.5 V to 5.5 V supply. These devices
AD5348: octal 12-bit DAC
incorporate an on-chip output buffer that can drive the output
Low power operation: 1.4 mA (max) at 3.6 V
to both supply rails, and also allow a choice of buffered or
Power-down to 120 nA at 3 V, 400 nA at 5 V
unbuffered reference input.
Guaranteed monotonic by design over all codes
Rail-to-rail output range: 0 V to VREF or 0 V to 2 × VREF
Power-on reset to 0 V
Simultaneous update of DAC outputs via LDAC pin
Asynchronous CLR facility
The AD5346/AD5347/AD5348 have a parallel interface. CS
selects the device and data is loaded into the input registers on
the rising edge of WR. A readback feature allows the internal
DAC registers to be read back through the digital port.
Readback
The GAIN pin on these devices allows the output range to be
Buffered/unbuffered reference inputs
set at 0 V to VREF or 0 V to 2 × VREF.
20 ns WR time
38-lead TSSOP/6 mm × 6 mm 40-lead LFCSP packaging
Temperature range: –40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Optical networking
Automatic test equipment
Mobile communications
Programmable attenuators
Input data to the DACs is double-buffered, allowing simultane-
ous update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the input register and the DAC register to all zeros.
These devices also incorporate a power-on reset circuit that
ensures that the DAC output powers on to 0 V and remains
there until valid data is written to the device.
All three parts are pin compatible, which allows users to select
the amount of resolution appropriate for their application
without redesigning their circuit board.
Industrial process control
FUNCTIONAL BLOCK DIAGRAM
VDD AGND DGND
VREFAB
VREFCD
BUF
GAIN
DB1... 1
DB0
CS
RD
WR
A2
A1
A0
CLR
LDAC
INTER-
FACE
LOGIC
AD5348
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
STRING
DAC A
STRING
DAC B
STRING
DAC C
STRING
DAC D
STRING
DAC E
STRING
DAC F
STRING
DAC G
STRING
DAC H
POWER-ON
RESET
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
VOUTA
VOUTB
VOUTC
VOUTD
VOUTE
VOUTF
VOUTG
VOUTH
POWER-DOWN
LOGIC
1 Protected by U.S. Patent No. 5,969,657.
VREFGH
Figure 1.
VREFEF
PD
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com









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AD5346 Даташит, Описание, Даташиты
AD5346/AD5347/AD5348
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Functional Block Diagram .......................................................... 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
AC Characteristics........................................................................ 5 
Timing Characteristics ................................................................ 5 
Absolute Maximum Ratings............................................................ 7 
ESD Caution.................................................................................. 7 
Pin Configurations and Function Descriptions ........................... 8 
Terminology .................................................................................... 11 
Typical Performance Characteristics ........................................... 13 
Functional Description .................................................................. 17 
Digital-to-Analog Section ......................................................... 17 
Resistor String ............................................................................. 17 
DAC Reference Input................................................................. 17 
Output Amplifier........................................................................ 17 
REVISION HISTORY
6/15—Rev. 0 to Rev. A
Changes to Figure 6.......................................................................... 8
Changes to Figure 8.......................................................................... 9
Changes to Figure 10...................................................................... 10
Deleted Driving VDD from the Reference Voltage Section and
Figure 42; Renumbered Sequentially ........................................... 20
Deleted Table 9 and Table 10; Renumbered Sequentially ......... 23
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 24
11/03—Revision 0: Initial Version
Data Sheet
Parallel Interface......................................................................... 17 
Power-On Reset.......................................................................... 18 
Power-Down Mode .................................................................... 18 
Suggested Data Bus Formats..................................................... 19 
Applications Information .............................................................. 20 
Typical Application Circuits ..................................................... 20 
Bipolar Operation Using the AD5346/AD5347/AD5348..... 20 
Decoding Multiple AD5346/AD5347/AD5348s.................... 21 
AD5346/AD5347/AD5348 as Digitally Programmable
Window Detectors ...................................................................... 21 
Programmable Current Source ................................................ 21 
Coarse and Fine Adjustment Using the
AD5346/AD5347/AD5348 ....................................................... 22 
Power Supply Bypassing and Grounding................................ 22 
Outline Dimensions ....................................................................... 23 
Ordering Guide .......................................................................... 24 
Rev. A | Page 2 of 24









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AD5346 Даташит, Описание, Даташиты
Data Sheet
AD5346/AD5347/AD5348
SPECIFICATIONS
VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter2
DC PERFORMANCE3, 4
AD5346
Resolution
Relative Accuracy
Differential Nonlinearity
AD5347
Resolution
Relative Accuracy
Differential Nonlinearity
AD5348
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband5
Min
Upper Deadband5
Offset Error Drift6
Gain Error Drift6
DC Power Supply Rejection Ratio6
DC Crosstalk6
DAC REFERENCE INPUT6
VREF Input Range
VREF Input Range
VREF Input Impedance
1
0.25
Reference Feedthrough
Channel-to-Channel Isolation
OUTPUT CHARACTERISTICS6
Minimum Output Voltage4, 7
Maximum Output Voltage4, 7
DC Output Impedance
Short Circuit Current
Power-Up Time
B Version1
Typ Max Unit
8
±0.15
±0.02
10
±0.5
±0.05
12
±2
±0.2
±0.4
±0.1
10
10
–12
–5
–60
200
>10
90
45
–90
–75
0.001
VDD
0.001
0.5
25
16
2.5
5
Bits
±1 LSB
±0.25 LSB
Bits
±4 LSB
±0.5 LSB
Bits
±16 LSB
±1 LSB
±3 % of FSR
±1 % of FSR
60 mV
60 mV
ppm of
FSR/°C
ppm of
FSR/°C
dB
μV
VDD V
VDD V
dB
dB
V min
V max
Ω
mA
mA
μs
μs
Test Conditions/Comments
Guaranteed monotonic by design over all codes
Guaranteed monotonic by design over all codes
Guaranteed monotonic by design over all codes
Lower deadband exists only if offset error is
negative
VDD = 5 V; upper deadband exists only if VREF = VDD
∆VDD = ±10%
RL = 2 kΩ to GND, 2 kΩ to VDD; CL = 200 pF to GND;
Gain = +1
Buffered reference mode
Unbuffered reference mode
Buffered reference mode and power-down mode
Gain = +1; input impedance = RDAC
Gain = +2; input impedance = RDAC
Frequency = 10 kHz
Frequency = 10 kHz
Rail-to-rail operation
VDD = 5 V
VDD = 3 V
Coming out of power-down mode; VDD = 5 V
Coming out of power-down mode; VDD = 3 V
Rev. A | Page 3 of 24










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