AX-SFEU PDF даташит
Спецификация AX-SFEU изготовлена «ON Semiconductor» и имеет функцию, называемую «Transceiver IC». |
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Детали детали
Номер произв | AX-SFEU |
Описание | Transceiver IC |
Производители | ON Semiconductor |
логотип |
20 Pages
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AX-SFEU, AX-SFEU-API
Ultra-Low Power,
AT Command / API Controlled,
Sigfox) Compliant
Transceiver IC for Up-Link
and Down-Link
www.onsemi.com
OVERVIEW
Circuit Description
AX−SFEU and AX−SFEU−API are ultra−low power
single chip solutions for a node on the Sigfox network with
both up− and down−link functionality. The AX−SFEU chip
is delivered fully ready for operation and contains all the
necessary firmware to transmit and receive data from the
Sigfox network in Europe. It connects to the customer
product using a logic level RS232 UART. AT commands are
used to send frames and configure radio parameters.
The AX−SFEU−API variant is intended for customers
wishing to write their own application software based on the
AX−SF−LIB−1−GEVK library.
Features
Functionality and Ecosystem
• Sigfox up−link and down−link functionality controlled
by AT commands or API
• The AX−SFEU and AX−SF−API ICs are part of a
whole development and product ecosystem available
from ON Semiconductor for any Sigfox requirement.
Other parts of the ecosystem include
♦ Ready to go development kit
DVK−SFEU−[API]−1−GEVK including a 2 year
Sigfox subscription
♦ Sigfox Ready® certified reference design for the
AX−SFEU and AX−SFEU−API ICs
♦ AX−SF10−MINI21−868−B1 and
AX−SF10−ANT21−868−B1, Sigfox compliant SMT
modules based on AX−SFEU with 50 W pads or chip
antenna. Not available for AX−SFEU−API
General Features
• QFN40 5 mm x 7 mm package
• Supply range 1.8 V* − 3.6 V
• −40°C to 85°C
• Temperature sensor
• Supply voltage measurements
*The device is operational from 1.8 V to 3.6 V. However, a supply
voltage below 2.0 V is considered an extreme condition.
Details see Table 4.
• 10 GPIO pins
♦ 4 GPIO pins with selectable voltage measure
functionality, differential (1 V or 10 V range) or
single ended (1 V range) with 10 bit resolution
♦ 2 GPIO pins with selectable sigma delta DAC
output functionality
♦ 2 GPIO pins with selectable output clock
♦ 3 GPIO pins selectable as SPI master interface
♦ Integrated RX/TX switching with differential
antenna pins
Power Consumption
• Ultra−low Power Consumption:
♦ Charge required to send a Sigfox OOB packet at
14 dBm output power: 0.28 C
♦ Deepsleep mode current: 100 nA
♦ Sleep mode current: 1.3 mA
♦ Standby mode current: 0.5 mA
♦ Continuous radio RX−mode at 869.525 MHz :
10 mA
♦ Continuous radio TX−mode at 868.130 MHz
19 mA @ 0 dBm
49 mA @ 14 dBm
High Performance Narrow−band Sigfox RF Transceiver
• Receiver
♦ Carrier frequency 869.525 MHz
♦ Data−rate 600 bps FSK
♦ Sensitivity
−126 dBm @ 600 bps, 869.525 MHz, GFSK
♦ 0 dBm maximum input power
• Transmitter
♦ Carrier frequency 868.13 MHz
♦ Data−rate 100 bps PSK
♦ High efficiency, high linearity integrated power
amplifier
♦ Maximum output power 14 dBm
♦ Power level programmable in 1 dBm steps
Applications
Sigfox networks up−link and down−link.
© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 4
1
Publication Order Number:
AX−SFEU/D
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BLOCK DIAGRAM
CLKP
CLKN
ANTP
ANTN
AX−SFEU, AX−SFEU−API
AX−SFEU / AX−SFEU−API
TCXO
interface
RF synthesis
RX/TX
switch and
antenna
interface
Receive
Transmit
Communication
controller
CAL
FILT
UARTRX
UARTTX
GPIO[9:0]
RADIO_LED
CPU_LED
TX_LED
RX_LED
UART
GPIO
DAC
ADC
dedicated
status
outputs
CPU
power mode control
RAM
Program
memory
(FLASH)
Sigfox identity (ID, PAC)
Sigfox compliant
application
(AX−SFEU only)
Figure 1. Functional Block Diagram of the AX−SFEU / AX−SFEU−API
www.onsemi.com
2
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AX−SFEU, AX−SFEU−API
Table 1. PIN FUNCTION DESCRIPTIONS
Symbol
Pin(s)
Type
VDD_ANA
1P
GND
2P
ANTP
3A
ANTN
4A
NC 5 N
GND
6P
VDD_ANA
7P
GND
8P
FILT 9 A
L2 10 A
L1 11 A
NC 12 N
GPIO8
13 I/O/PU
GPIO7
14 I/O/PU
GPIO6
15 I/O/PU
GPIO5
16 I/O/PU
GPIO4
17 I/O/PU
CPU_LED
RADIO_LED
VTCXO
GPIO9
UARTTX
UARTRX
RX_LED
TX_LED
NC
RESET_N
18 O
19 O
20 O
21 I/O/PU
22 O
23 I/PU
24 O
25 O
26 PD
27 I/PU
GND
VDD_IO
GPIO0
28 P
29 P
30 I/O/A/PU
GPIO1
GPIO2
NC
NC
GPIO3
VDD_IO
CAL
NC
CLKN
31 I/O/A/PU
32 I/O/A/PU
33 N
34 N
35 I/O/A/PU
36 P
37 A
38 N
39 A
Description
Analog power output, decouple to neighboring GND
Ground, decouple to neighboring VDD_ANA
Differential antenna input/output
Differential antenna input/output
Do not connect
Ground, decouple to neighboring VDD_ANA
Analog power output, decouple to neighboring GND
Ground
Synthesizer filter
Must be connected to pin L1
Must be connected to pin L2
Do not connect
General purpose IO
General purpose IO, selectable SPI functionality (MISO)
General purpose IO, selectable SPI functionality (MOSI)
General purpose IO, selectable SPI functionality (SCK)
General purpose IO, selectable SD DAC functionality, selectable dock
functionality
CPU activity indicator
Radio activity indicator
TCXO power
General purpose IO, wakeup from deep sleep
UART transmit
UART receive
Receive activity indicator
Transmit activity indicator
Do not connect
Optional reset pin. Internal pull−up resistor is permanently enabled,
nevertheless it is recommended to connect this pin to VDD_IO if it is not used.
Ground
Unregulated power supply
General purpose IO, selectable ADC functionality, selectable SD DAC
functionality, selectable clock functionality
General purpose IO, selectable ADC functionality
General purpose IO, selectable ADC functionality
Do not connect
Do not connect
General purpose IO, selectable ADC functionality
Unregulated power supply
Connect to FILT as shown in the application diagram
Connect to Ground
TCXO interface
www.onsemi.com
3
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Номер в каталоге | Описание | Производители |
AX-SFEU | Transceiver IC | ON Semiconductor |
AX-SFEU-API | Transceiver IC | ON Semiconductor |
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