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UT01VS33D PDF даташит

Спецификация UT01VS33D изготовлена ​​​​«Aeroflex Circuit Technology» и имеет функцию, называемую «Voltage Supervisor».

Детали детали

Номер произв UT01VS33D
Описание Voltage Supervisor
Производители Aeroflex Circuit Technology
логотип Aeroflex Circuit Technology логотип 

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UT01VS33D Даташит, Описание, Даташиты
Standard Products
UT01VS33D Voltage Supervisor
Data Sheet
July 28, 2014
www.aeroflex.com/voltsupv
FEATURES
3.15V to 3.6V Operating voltage range
Power supply (VDD) monitor set by the internal voltage
reference at 3.08V
Precision Input Voltage Monitor using an internal 0.6V
voltage reference
Watchdog Timer Circuit monitoring activity on WDI input
- Nominal timeout 1.6s
RESET_OD output responding to the VDD monitor and the
manual reset input MR
- Nominal RESET_OD pulse width 200ms
RESET_OD level valid for VDD>=1.2V
Operating Temperature Range -55oC to +125oC
Low Power, Typical 400uA
Operational environment:
- Total dose: 300 krad(Si)
- SEL Immune: <110 MeV-cm2/mg @125oC
- SET Immune: <80 MeV-cm2/mg
Packaging options:
- 8-lead dual-in-line flatpack
Standard Microelectronics Drawing 5962-11213
- QML Q and V
INTRODUCTION
The UT01VS33D’s function is to monitor vital supply and signal
voltages in microprocessor systems. It provides for safe reset
during power up, power down and brownout conditions by using
an internal precision voltage reference.
The UT01VS33D monitors activity at an independent watchdog
input by employing an internal timer and a watchdog output that
goes low if the input is not toggled within 1.6s. It provides for
precision voltage threshold detection on an independent voltage
input which could be used for battery or supply-low monitoring
of a supply voltage other than VDD.
The UT01VS33D includes an active low manual reset with an
open drain output.
APPLICATIONS
Voltage Supervisor function for various systems including
microprocessors, microcontrollers, DSPs and FPGAs
Critical battery and power supply monitoring
Replacement of older discrete solutions to improve reliability,
accuracy and reduce complexity of the systems
MR
RESET &
DIGITAL CONTROL
VDD +
WDI TIMER
3.08 V
GND
0.6 V
VREF
WDI TRANSITION
DETECTOR
OSC
PFI +
WDO
RESET_OD
WDI
PFO
Figure 1. UT01VS33D Functional Block Diagram
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UT01VS33D Даташит, Описание, Даташиты
PIN DESCRIPTIONS
Number
1
2
3
4
5
6
7
Pins
MR
VDD
GND
PFI
PFO
WDI
RESET_OD
Type
Digital Input
Supply
Supply
Analog Input
Digital Output
Digital Input
Open Drain
Digital Output
Description
Manual Reset Input with an internal pull-up. Active low. MR low forces the reset
output RESET_OD low. Required minimum MR pulse width is 150ns. RESET_OD
is held low for duration of the reset timer.
Power supply. Operating voltage range is 3.15V to 3.6V. VDD level is monitored
internally by a dedicated comparator circuit, which employs an internal bandgap
voltage reference nominally equal to 1.25V. Every time VDD falls below the threshold
voltage, nominally 3.08V, RESET_OD and WDO outputs are forced low. (See WDO
and RESET_OD descriptions.) (Figure 4.)
Ground. This pin should be tied to ground and establishes the reference for voltage
detection.
Threshold detector input. Voltage on this input is fed directly to an internal
comparator where it is compared to the voltage reference of 0.6V. It can be used for
detection of low battery or power failure of voltage supplies other than VDD. When
voltage at PFI input drops below its threshold value of 0.6V, PFO output is forced low,
otherwise, stays high.
Threshold detector output. Active low. It responds directly to PFI input. If PFI
voltage is below the bandgap reference voltage, PFO is low. If PFI is above the
reference voltage, PFO output is high.
Watchdog timer input pin. This pin is typically used to monitor microprocessor
activity. It can assume three states: low, high and float. If WDI is floating or connected
to a high impedance three state buffer, the watchdog timer is not active, and the
corresponding watchdog output WDO is high. Watchdog timer is also not active any
time RESET_OD is low. Providing that RESET_OD is not asserted, any change of
state at WDI that is longer than 100ns will start the timer, or restart it, if the timer is
already running (Figure 3.). If there is no activity within the timeout period, nominally
1.6sec, the timer will stop running and WDO output will go low (Figure 3).
Reset output. Active low open drain output. This pin is pulled up with a resistor
consistant with the sink and voltage current as specified in the electrical characteristics
table. This output responds to both: VDD monitoring circuits and the manual reset
input MR.
On power up, RESET_OD is guaranteed to be logic low for all VDD values from 1.2V
up to the reset threshold, nominally 3.08V. Once this threshold is reached, an internal
RESET_OD timer is activated. During the countdown RESET_OD output is kept low.
It is raised high upon completion of countdown, typically after 200ms. If a brown out
condition occurs during the reset timer countdown, the reset timer would be reset and
another countdown would start after VDD levels were restored above the reset
threshold. On power down, when VDD falls below the threshold voltage, RESET_OD
goes low and is guaranteed to stay low until VDD drops below 1.2V.
If MR is asserted low, RESET_OD is forced low and the reset timer is kept reset.
When MR is released high, the timer is activated and RESET_OD is kept low until
completion of the reset timeout, when it is raised high.
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UT01VS33D Даташит, Описание, Даташиты
Number
8
Pins
WDO
Type
Digital Output
Description
Watchdog output. Active low. This pin is usually connected to a non-maskable
interrupt input of a microprocessor. On power up, WDO responds to VDD monitoring
circuitry. It stays low until the reset threshold, 3.08V nominally, is reached. At that
point, WDO is raised high. The internal watchdog timer is activated after RESET_OD
is released. If there is no activity on WDI input, WDO goes low after the watchdog
timer times out, which is typically after 1.6sec. Any activity on WDI will force WDO
output to go high and the watchdog timer will be activated. If WDI is floating or
connected to a high impedance buffer output, the timer is kept in a reset state and
WDO stays high. When VDD drops below 3.08V, WDO goes low regardless of
whether the watchdog timer has timed out or not. RESET_OD goes low
simultaneously which prevents an interrupt.
If WDI input is left unconnected, WDO can be used as a low line output. Since a
floating WDI disables the internal watchdog timer, WDO goes low when VDD drops
below 3.08V, thus, functioning as a low line output. (Figure 4.)
MR 1
8
VDD 2
7
UT01VS33D
GND 3
6
PFI 4
5
WDO
RESET_OD
WDI
PFO
Figure 2. UT01VS33D Pin Configuration
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