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UT8SF2M40 PDF даташит

Спецификация UT8SF2M40 изготовлена ​​​​«Aeroflex Circuit Technology» и имеет функцию, называемую «80Megabit Flow-thru SSRAM».

Детали детали

Номер произв UT8SF2M40
Описание 80Megabit Flow-thru SSRAM
Производители Aeroflex Circuit Technology
логотип Aeroflex Circuit Technology логотип 

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UT8SF2M40 Даташит, Описание, Даташиты
Standard Products
UT8SF2M40 80Megabit Flow-thru SSRAM
Preliminary Datasheet
www.aeroflex.com/memories
April 2015
FEATURES
Synchronous SRAM organized as 2Meg words x 40bit
Continuous Data Transfer (CDT) architecture eliminates
wait states between read and write operations
Supports 40MHz to 80MHz bus operations
Internally self-timed output buffer control eliminates the
need for synchronous output enable
Registered inputs and outputs for flow-thru operation
Single 2.5V to 3.3V supply
Clock-to-output time
- Clk to Q = 12ns
Clock Enable (CEN) pin to enable clock and suspend
operation
Synchronous self-timed writes
Three Chip Enables (CS0, CS1, CS2) for simple depth
expansion
"ZZ" Sleep Mode option for partial power-down
"SHUTDOWN" Mode option for deep power-down
Four Word Burst Capability--linear or interleaved
Operational Environment
- Total Dose: 100 krad(Si)
- SEL Immune: 100MeV-cm2/mg
- SEU error rate: 1.7x10-6 errors/bit-day
Package options:
- 288-lead CLGA, CCGA, and CBGA
Standard Microelectronics Drawing (SMD) 5962-TBD
- QMLQ and Q+ pending
INTRODUCTION
The UT8SF2M40 is a high performance 83,886,080-bit
synchronous static random access memory (SSRAM) device
that is organized as 2M words of 40 bits. This device is
equipped with three chip selects (CS0, CS1, and CS2), a write
enable (WE), and an output enable (OE) pin, allowing for
significant design flexibility without bus contention. The
device supports a four word burst function using (ADV_LD).
All synchronous inputs are registered on the rising edge of the
clock provided the Clock Enable (CEN) input is enabled LOW.
Operations are suspended when CEN is disabled HIGH and the
previous operation is extended. Write operation control signals
are WE and six byte write enables BWE[4:0]. All write
operations are performed by internal self-timed circuitry.
For easy bank selection, three synchronous Chip Enables
(CS0, CS1, CS2) and an asynchronous Output Enable (OE)
provide for output tri-state control. The output drivers are
synchronously tri-stated during the data portion of a write
sequence to avoid bus contention.
36-00-01-005
Ver. 1.0.0
1 Aeroflex Microelectronics Solutions - HiRel









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UT8SF2M40 Даташит, Описание, Даташиты
ADDR
CMD
CLK
User Command Interface Logic
Housekeeping,
and Fault Logic
Main Memory Array 2Meg x 40
Write
Address and
Command
Queue
Write Data
Coherency Logic
Pipeline
Register
Write Data
Steering Logic
Stall Cycle
Registers
Write Data
Queue
Read Data
Steering and
Fault Logic
Figure 1. UT8SF2M40 Block Diagram
DIN
QOUT
36-00-01-005
Ver. 1.0.0
2 Aeroflex Microelectronics Solutions - HiRel









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UT8SF2M40 Даташит, Описание, Даташиты
NAME
CS0
CS1
CS2
A[20:0]
BWE[4:0]
WE
ADV_LD
CLK
OE
CEN
DQ[47:0]
RESET
Table 1: Pin Definitions
DESCRIPTION
Chip Enable 0, Input, Active LOW: Sampled on the rising edge of CLK.
Used in conjunction with CS1 and CS2 to select or deselect the device.
Chip Enable 1 Input, Active HIGH: Sampled on the rising edge of CLK.
Used in conjunction with CS0 and CS2 to select or deselect the device.
Chip Enable 2 Input, Active LOW: Sampled on the rising edge of CLK.
Used in conjunction with CS0 and CS1 to select or deselect the device.
Address Inputs: Sampled at the rising edge of the CLK. A[1:0] is fed to the
two-bit burst counter.
Byte Write Enable, Active LOW: Qualified with WE, allows writes to each
of six bytes of memory when active, and masks input data when disabled.
Write Enable Input, Active LOW: Sampled on the rising edge of CLK if
CEN is active LOW. This signal must be enabled LOW to initiate a write
sequence.
Advance/Load Input: Advances the on-chip address counter or loads a new
address. When HIGH (and CEN is enabled LOW) the internal burst counter
is advanced. When LOW, a new address can be loaded into the device for an
access. After deselection, drive ADV_LD LOW to load a new address.
Clock Input: Used to capture all synchronous inputs to the device. CLK is
qualified with CEN. CLK is only recognized if CEN is active LOW.
Output Enable, Asynchronous Input, Active LOW: Combined with the
synchronous logic block inside the device to control the direction of the I/O
pins. When LOW, the I/O pins are enabled to behave as outputs. When
disabled HIGH, I/O pins are tri-stated, and act as input data pins. OE is
masked during the data portion of a write sequence, during the first clock
when emerging from a deselected state and when the device is deselected.
Clock Enable Input, Active LOW: When enabled LOW, the clock signal is
recognized by the SSRAM. When deasserted HIGH, the clock signal is
masked. Because deasserting CEN does not deselect the device, CEN can be
used to extend the previous cycle when required.
Bidirectional Data I/Os: As inputs, DQ[47:0] feed into an on-chip data
register that is triggered by the rising edge of CLK. As outputs, DQ[47:0]
delivers the data contained in the memory location specified by the addresses
presented during the previous clock rise of the read cycle. The direction of
the pins is controlled by OE. When OE is enabled LOW, the pins behave as
outputs. When HIGH, DQs are placed in a tri-state condition. The outputs
are automatically tri-stated during the data portion of a write sequence,
during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE. Aeroflex recommends
connecting all DQ pins to either VDDQ or VSS through a >10kresistor.
Reset Input, Active Low: Resets device to known configuration. Reset is
required at initial power-up, after exiting shutdown mode, or after any power
interruption.
TYPE
Input-Synchronous
Input-Synchronous
Input-Synchronous
Input-Synchronous
Input-Synchronous
Input-Synchronous
Input-Synchronous
Input-Clock
Input-Asynchronous
Input-Synchronous
I/O-Synchronous
Input-ASynchronous
36-00-01-005
Ver. 1.0.0
3 Aeroflex Microelectronics Solutions - HiRel










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Номер в каталогеОписаниеПроизводители
UT8SF2M4080Megabit Flow-thru SSRAMAeroflex Circuit Technology
Aeroflex Circuit Technology

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