ADuM4153 Datasheet PDF ( Pinout ) - SPIsolator Digital Isolators

ADuM4153 Datasheet PDF - Analog Devices

Part Number	*ADuM4153*
Description	SPIsolator Digital Isolators
Manufacturers	Analog Devices
Logo
There is a preview and ADuM4153 download ( pdf file ) link at the bottom of this page. Total 22 Pages

Preview 1 page

No Preview Available ! ADuM4153 datasheet, circuit

Data Sheet

5 kV, 7-Channel,

SPIsolator Digital Isolators for SPI

ADuM4151/ADuM4152/ADuM4153

FEATURES

Supports up to 17 MHz SPI clock speed

4 high speed, low propagation delay, SPI signal isolation

channels

Three 250 kbps data channels

20-lead SOIC_IC package with 8.3 mm creepage

High temperature operation: 125°C

High common-mode transient immunity: >25 kV/µs

Safety and regulatory approvals

UL recognition per UL 1577

5000 V rms for 1 minute SOIC long package

CSA Component Acceptance Notice 5A

VDE certificate of conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

Maximum working insulation voltage (VIORM): 849 V peak

APPLICATIONS

Industrial programmable logic controllers (PLCs)

Sensor isolation

GENERAL DESCRIPTION

The ADuM4151/ADuM4152/ADuM41531 are 7-channel,

SPIsolator™ digital isolators optimized for isolated serial peripheral

interfaces (SPIs). Based on the Analog Devices, Inc., iCoupler®

chip scale transformer technology, the low propagation delay in

the CLK, MO/SI, MI/SO, and SS SPI bus signals supports SPI

clock rates of up to 17 MHz. These channels operate with 14 ns

propagation delay and 1 ns jitter to optimize timing for SPI.

The ADuM4151/ADuM4152/ADuM4153 isolators also provide

three additional independent low data rate isolation channels in

three different channel direction combinations. Data in the slow

channels is sampled and serialized for a 250 kbps data rate with

up to 2.5 µs of jitter in the low speed channels.

FUNCTIONAL BLOCK DIAGRAMS

VDD1 1

GND1 2

MCLK 3

MO 4

MI 5

MSS 6

ADuM4151

ENCODE

DECODE

ENCODE

VIA 7

VIB 8

VOC 9

CONTROL

BLOCK

GND1 10

DECODE

ENCODE

DECODE

CONTROL

BLOCK

20 VDD2

19 GND2

18 SCLK

17 SI

16 SO

15 SSS

14 VOA

13 VOB

12 VIC

11 GND2

Figure 1. ADuM4151 Functional Block Diagram

VDD1 1

GND1 2

MCLK 3

MO 4

MI 5

MSS 6

ADuM4152

ENCODE

DECODE

ENCODE

VIA 7

VOB 8

VOC 9

CONTROL

BLOCK

GND1 10

DECODE

ENCODE

DECODE

CONTROL

BLOCK

20 VDD2

19 GND2

18 SCLK

17 SI

16 SO

15 SSS

14 VOA

13 VIB

12 VIC

11 GND2

Figure 2. ADuM4152 Functional Block Diagram

VDD1 1

GND1 2

MCLK 3

MO 4

MI 5

MSS 6

ADuM4153

ENCODE

DECODE

ENCODE

VOA 7

VOB 8

VOC 9

CONTROL

BLOCK

GND1 10

DECODE

ENCODE

DECODE

CONTROL

BLOCK

20 VDD2

19 GND2

18 SCLK

17 SI

16 SO

15 SSS

14 VIA

13 VIB

12 VIC

11 GND2

Figure 3. ADuM4153 Functional Block Diagram

1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,262,600; and 7,075,329. Other patents are pending.

Rev. A

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

Data Sheet

ADuM4151/ADuM4152/ADuM4153

ELECTRICAL CHARACTERISTICS—3.3 V OPERATION

All typical specifications are at TA = 25°C and VDD1 = VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire

recommended operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching

specifications are tested with CL =15 pF and CMOS signal levels, unless otherwise noted.

Table 4. Switching Specifications

Parameter

MCLK, MO, SO

SPI Clock Rate

Data Rate Fast (MO, SO)

Propagation Delay

Pulse Width

Pulse Width Distortion

Codirectional Channel Matching1

Jitter, High Speed

MSS

Data Rate Fast

Propagation Delay

Pulse Width

Pulse Width Distortion

Setup Time2

Jitter, Low Speed

VIA, VIB, VIC

Data Rate Slow

Propagation Delay

Pulse Width

Jitter, Low Speed

VIx3 Minimum Input Skew4

Symbol

SPIMCLK

DRFAST

tPHL, tPLH

PWD

tPSKCD

JHS

DRFAST

tPHL, tPLH

PWD

MSSSETUP

JLS

DRSLOW

tPHL, tPLH

JLS

tVIx SKEW3

A Grade

Min Typ Max

100

1.5

2.5

250

0.1 2.6

2.5

B Grade

Min Typ Max

12.5

2.5

250

0.1 2.6

2.5

Unit

MHz

Mbps

kbps

µs

Test Conditions/Comments

Within PWD limit

50% input to 50% output

Within PWD limit

|tPLH − tPHL|

Within PWD limit

50% input to 50% output

Within PWD limit

|tPLH − tPHL|

Within PWD limit

50% input to 50% output

Within PWD limit

|tPLH − tPHL|

1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.

2 The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output

ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.

3 VIx = VIA, VIB, or VIC.

4 An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the

leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.

Table 5. Supply Current

Device Number

ADuM4151

ADuM4152

ADuM4153

Symbol

IDD1

IDD2

IDD1

IDD2

IDD1

IDD2

1 MHz, A Grade/B Grade

Min Typ Max

3.8 7

5.1 8

3.7 6.5

5.2 8

3.7 6.5

5.2 9

17 MHz, B Grade

Min Typ Max Unit Test Conditions/Comments

10.5 18