DataSheet26.com

74LV138 PDF даташит

Спецификация 74LV138 изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «3-to-8 line decoder/demultiplexer».

Детали детали

Номер произв 74LV138
Описание 3-to-8 line decoder/demultiplexer
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

16 Pages
scroll

No Preview Available !

74LV138 Даташит, Описание, Даташиты
74LV138
3-to-8 line decoder/demultiplexer; inverting
Rev. 4 — 4 March 2016
Product data sheet
1. General description
The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC138 and 74HCT138.
The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted
address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive
active LOW outputs (Y0 to Y7).
There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3).
Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the device to a 1-of-32
(5 lines to 32 lines) decoder with just four 74LV138 devices and one inverter. The
74LV138 can be used as an eight output demultiplexer by using one of the active LOW
enable inputs as the data input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their appropriate active HIGH or LOW state.
2. Features and benefits
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 C
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C









No Preview Available !

74LV138 Даташит, Описание, Даташиты
NXP Semiconductors
74LV138
3-to-8 line decoder/demultiplexer; inverting
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74LV138D
40 C to +125 C SO16
plastic small outline package; 16 leads;
body width 3.9 mm
74LV138DB
40 C to +125 C SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
74LV138PW
40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
74LV138BQ
40 C to +125 C
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
Version
SOT109-1
SOT338-1
SOT403-1
SOT763-1
4. Functional diagram



 (
 (
 (
Fig 1. Logic symbol
$ < 
$ < 
$ < 
< 
< 
< 
< 
< 
PQD
';  

 

*





 
 
  
 
 
D
Fig 2. IEC logic symbol
;<  

 

 

 
 
  
 

(1


PQD
E
Fig 3. Functional diagram
74LV138
Product data sheet
 $
 $
 $
WR
'(&2'(5
(1$%/(
(;,7,1*
 (
 (
 (
< 
< 
< 
< 
< 
< 
< 
< 
PQD
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 4 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 16









No Preview Available !

74LV138 Даташит, Описание, Даташиты
NXP Semiconductors
74LV138
3-to-8 line decoder/demultiplexer; inverting
5. Pinning information
5.1 Pinning
$ 
$ 
$ 
( 
( 
( 
< 
*1' 
 9&&
 <
 <
 <

 <
 <
 <
 <
DDG
Fig 4. Pin configuration SO16 and (T)SSOP16
WHUPLQDO
LQGH[DUHD
/9
$ 
$ 
( 
( 
( 
< 
9&& 
 <
 <
 <
 <
 <
 <
DDK
7UDQVSDUHQWWRSYLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to VCC.
Fig 5. Pin configuration DHVQFN16
5.2 Pin description
Table 2.
Symbol
A0
A1
A2
E1
E2
E3
GND
Y0 to Y7
VCC
Pin description
Pin
1
2
3
4
5
6
8
15, 14, 13, 12, 11, 10, 9, 7
16
Description
address input
address input
address input
enable input (active LOW)
enable input (active LOW)
enable input (active HIGH)
ground (0 V)
output
supply voltage
74LV138
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 4 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3 of 16










Скачать PDF:

[ 74LV138.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
74LV132Quad 2-input NAND Schmitt-triggerPhilips
Philips
74LV132AQUADRUPLE 2-INPUT NAND GATESDiodes
Diodes
74LV1383-to-8 line decoder/multiplexer; invertingPhilips
Philips
74LV1383-to-8 line decoder/demultiplexerNXP Semiconductors
NXP Semiconductors

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск