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IS42VM16200D PDF даташит

Спецификация IS42VM16200D изготовлена ​​​​«ISSI» и имеет функцию, называемую «1M x 16Bits x 2Banks Low Power Synchronous DRAM».

Детали детали

Номер произв IS42VM16200D
Описание 1M x 16Bits x 2Banks Low Power Synchronous DRAM
Производители ISSI
логотип ISSI логотип 

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IS42VM16200D Даташит, Описание, Даташиты
IS42/45SM/RM/VM16200D
1M x 16Bits x 2Banks Low Power Synchronous DRAM
Description
These IS42SM/RM/VM16200D are low power 33,554,432 bits CMOS Synchronous DRAM organized as 2 banks of 1,048,576 words x 16
bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input
and output voltage levels are compatible with LVCMOS.
Features
JEDEC standard 3.3V, 2.5V, 1.8V power supply
Auto refresh and self refresh
All pins are compatible with LVCMOS interface
4K refresh cycle / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full Page for Sequential Burst
- 4 or 8 for Interleave Burst
Programmable CAS Latency : 2,3 clocks
All inputs and outputs referenced to the positive edge of the
system clock
Data mask function by DQM
Internal dual banks operation
Burst Read Single Write operation
Special Function Support
- PASR(Partial Array Self Refresh)
- Auto TCSR(Temperature Compensated Self Refresh)
- Programmable Driver Strength Control
- Full Strength or 1/2, 1/4, of Full Strength
- Deep Power Down Mode
Automatic precharge, includes CONCURRENT Auto Precharge
Mode and controlled Precharge
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev. A | November 2015
www.issi.com - [email protected]
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IS42VM16200D Даташит, Описание, Даташиты
IS42/45SM/RM/VM16200D
Figure1: 54Ball FBGA Ball Assignment
1
2
3 456 7
8
9
A VSS DQ15 VSSQ
B DQ14 DQ13 VDDQ
C DQ12 DQ11 VSSQ
D DQ10 DQ9 VDDQ
E DQ8 NC VSS
F UDQM CLK CKE
G NC NC A9
H A8 A7 A6
J
VSS A5
A4
VDDQ DQ0 VDD
VSSQ DQ2 DQ1
VDDQ DQ4 DQ3
VSSQ DQ6 DQ5
VDD LDQM DQ7
/CAS /RAS /WE
BA NC /CS
A0 A1 A10
A3 A2 VDD
[Top View]
Rev. A | November 2015
www.issi.com - [email protected]
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IS42VM16200D Даташит, Описание, Даташиты
Table2: Pin Descriptions
Pin
Pin Name
CLK System Clock
CKE Clock Enable
/CS Chip Select
BA Bank Address
A0~A10
/RAS, /CAS, /WE
LDQM,UDQM
DQ0~DQ15
VDD/VSS
VDDQ/VSSQ
NC
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
IS42/45SM/RM/VM16200D
Descriptions
The system clock input. All other inputs are registered to the
SDRAM on the rising edge CLK.
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
Enable or disable all inputs except CLK, CKE and DQM.
Selects bank to be activated during RAS activity.
Selects bank to be read/written during CAS activity.
Row Address
Column Address
Auto Precharge
: RA0~RA10
: CA0~CA8
: A10
RAS, CAS and WE define the operation.
Refer function truth table for details.
Controls output buffers in read mode and masks input data in
write mode.
Data input/output pin.
Power supply for internal circuits and input buffers.
Power supply for output buffers.
No connection.
Rev. A | November 2015
www.issi.com - [email protected]
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