54191 PDF даташит
Спецификация 54191 изготовлена «Motorola Semiconductors» и имеет функцию, называемую «PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS». |
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Детали детали
Номер произв | 54191 |
Описание | PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS |
Производители | Motorola Semiconductors |
логотип |
10 Pages
No Preview Available ! |
PRESETTABLE BCD/DECADE
UP/DOWN COUNTERS
PRESETTABLE 4-BIT BINARY
UP/DOWN COUNTERS
The SN54 / 74LS190 is a synchronous UP/ DOWN BCD Decade (8421)
Counter and the SN54/ 74LS191 is a synchronous UP / DOWN Modulo-16
Binary Counter. State changes of the counters are synchronous with the
LOW-to-HIGH transition of the Clock Pulse input.
An asynchronous Parallel Load (PL) input overrides counting and loads the
data present on the Pn inputs into the flip-flops, which makes it possible to use
the circuits as programmable counters. A Count Enable (CE) input serves as
the carry / borrow input in multi-stage counters. An Up / Down Count Control
(U/D) input determines whether a circuit counts up or down. A Terminal Count
(TC) output and a Ripple Clock (RC) output provide overflow/underflow
indication and make possible a variety of methods for generating
carry / borrow signals in multistage counter applications.
• Low Power . . . 90 mW Typical Dissipation
• High Speed . . . 25 MHz Typical Count Frequency
• Synchronous Counting
• Asynchronous Parallel Load
• Individual Preset Inputs
• Count Enable and Up/ Down Control Inputs
• Cascadable
• Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC
16
P0
15
CP
14
RC
13
TC
12
PL
11
P2
10
P3
9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
P1
2
Q1
3
Q0
4
CE
5
U/D
6
Q2
7
Q3
8
GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
CE Count Enable (Active LOW) Input
1.5 U.L.
0.7 U.L.
CP Clock Pulse (Active HIGH going edge) Input 0.5 U.L. 0.25 U.L.
U / D Up/Down Count Control Input
0.5 U.L.
0.25 U.L.
PL Parallel Load Control (Active LOW) Input
0.5 U.L.
0.25 U.L.
Pn Parallel Data Inputs
Qn Flip-Flop Outputs (Note b)
RC Ripple Clock Output (Note b)
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
TC Terminal Count Output (Note b)
10 U.L. 5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
FAST AND LS TTL DATA
5-341
SN54/74LS190
SN54/74LS191
PRESETTABLE BCD/ DECADE
UP/ DOWN COUNTERS
PRESETTABLE 4-BIT BINARY
UP/ DOWN COUNTERS
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
11 15 1 10 9
5
4
14
PL
U/D
P0 P1 P2
P3
RC
CE
CP
Q0 Q1
TC
Q2 Q3
32 6 7
VCC = PIN 16
GND = PIN 8
13
12
No Preview Available ! |
SN54/74LS190 • SN54/74LS191
STATE DIAGRAMS
0123
15
14
13
12 11 10
9
LS190
4
5
6
7
8
UP:
DOWN:
LS190
⋅ ⋅TC = Q0 Q3 (U/D)
⋅ ⋅ ⋅ ⋅TC = Q0 Q1 Q2 Q3 (U/D)
UP:
DOWN:
LS191
⋅ ⋅ ⋅ ⋅TC = Q0 Q1 Q2 Q3 (U/D)
⋅ ⋅ ⋅ ⋅TC = Q0 Q1 Q2 Q3 (U/D)
COUNT UP
COUNT DOWN
0123
15
14
13
12 11 10
9
LS191
4
5
6
7
8
LOGIC DIAGRAMS
CP U/D
14 5
P0
15
CE
4
P1
1
P2
10
P3
9
PL
11
13 12
RC TC
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
J CLOCK K
PRESET CLEAR
QQ
3
Q0
J CLOCK K
PRESET CLEAR
QQ
J CLOCK K
PRESET CLEAR
QQ
26
Q1
Q2
DECADE COUNTER
LS190
J CLOCK K
PRESET CLEAR
QQ
7
Q3
FAST AND LS TTL DATA
5-342
No Preview Available ! |
SN54/74LS190 • SN54/74LS191
LOGIC DIAGRAMS (continued)
CP U/D
14
5
P0
15
CE
4
P1
1
P2
10
P3
9
PL
11
13
12
RC
TC
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
J CLOCK K
PRESET CLEAR
QQ
3
Q0
J CLOCK K
PRESET CLEAR
QQ
2
Q1
J CLOCK K
PRESET CLEAR
QQ
6
Q2
BINARY COUNTER
LS191
J CLOCK K
PRESET CLEAR
QQ
7
Q3
FAST AND LS TTL DATA
5-343
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54190 | PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS | Motorola Semiconductors |
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