25L3205 PDF даташит
Спецификация 25L3205 изготовлена «Macronix International» и имеет функцию, называемую «MX25L3205». |
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Детали детали
Номер произв | 25L3205 |
Описание | MX25L3205 |
Производители | Macronix International |
логотип |
30 Pages
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MX25L3205
FEATURES
Macronix NBitTM Memory Family
32M-BIT [x 1] CMOS SERIAL eLiteFlashTM MEMORY
GENERAL
• Serial Peripheral Interface (SPI) compatible -- Mode 0
and Mode 3
• 33,554,432 x 1 bit structure
• 64 Equal Sectors with 64K byte each
- Any sector can be erased
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
- Fast access time: 50MHz serial clock (30pF + 1TTL
Load)
- Fast program time: 3ms/page (typical, 256-byte per
page)
- Fast erase time: 1s/sector (typical, 64K-byte per
sector) and 64s/chip (typical)
- Acceleration mode:
- Program time: 2.4ms/page (typical)
- Erase time: 0.8s/sector (typical) and 51s/chip
(typical)
• Low Power Consumption
- Low active read current: 30mA (max.) at 50MHz
- Low active programming current: 30mA (max.)
- Low active erase current: 38mA (max.)
- Low standby current: 50uA (max.)
- Deep power-down mode 1uA (typical)
• Minimum 10K erase/program cycle for array
• Minimum 100K erase/program cycle for additional 4Kb
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected
sector
- Automatically programs and verifies data at selected
page by an internal algorithm that automatically times
the program pulse widths (Any page to be programed
should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
- REMS command, ADD=00H will output the
manufacturer's ID first and ADD=01H will output device
ID first
• Additional 4Kb sector independent from main memory
for parameter storage to eliminate EEPROM from
system
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI Input
- Serial Data Input
• SO/PO7
- Serial Data Output or Parallel mode Data output/input
• WP#/ACC Pin
- Hardware write protection and Program/erase accel-
eration
• HOLD# pin
- pause the chip without diselecting the chip (not for
paralled mode, please connect HOLD# pin to VCC dur-
ing parallel mode)
• PO0~PO6
- for parallel mode data output/input
• PACKAGE
- 16-pin SOP (300mil)
P/N: PM1169
REV. 1.0, JUL. 15, 2005
1
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MX25L3205
GENERAL DESCRIPTION
The MX25L3205 is a CMOS 33,554,432 bit serial
eLiteFlashTM Memory, which is configured as 4,194,304 x
8 internally. The MX25L3205 features a serial peripheral
interface and software protocol allowing operation on a
simple 3- wire bus. The three bus signals are a clock input
(SCLK), a serial data input (SI), and a serial data output
(SO). SPI access to the device is enabled by CS# input.
The MX25L3205 provide sequential read operation on
whole chip. User may start to read from any byte of the
array. While the end of the array is reached, the device will
wrap around to the beginning of the array and continuously
outputs data until CS# goes high.
After program/erase command is issued, auto program/
erase algorithms which program/erase and verify the
specified page locations will be executed. Program com-
mand is executed on a page (256 bytes) basis, and erase
command is executed on both chip and sector (64K bytes)
basis.
To provide user with ease of interface, a status register is
included to indicate the status of the chip. The status read
command can be issued to detect completion and error
flag status of a program or erase operation.
To increase user's factory throughputs, a parallel mode is
provided. The performance of read/program is dramatically
improved than serial mode on programmer machine.
When the device is not in operation and CS# is high, it is
put in standby mode and draws less than 50uA DC current.
The additional 4Kb sector with 100K erase/program endur-
ance cycles is suitable for parameter storage and replaces
the EEPROM on system.
The MX25L3205 utilizes MXIC's proprietary memory cell
which reliably stores memory contents even after 10K
program and erase cycles.
PIN CONFIGURATIONS
16-PIN SOP (300 mil)
HOLD#
VCC
NC
PO2
PO1
PO0
CS#
SO/PO7
1
2
3
4
5
6
7
8
16 SCLK
15 SI
14 PO6
13 PO5
12 PO4
11 PO3
10 GND
9 WP#/ACC
P/N: PM1169
PIN DESCRIPTION
SYMBOL DESCRIPTION
CS# Chip Select
SI Serial Data Input
SO/PO7(1) Serial Data Output or Parallel Data
output/input
SCLK
Clock Input
HOLD#(2) Hold, to pause the serial communication
(HOLD# is not for parallel mode)
WP#/ACC Write Protection: connect to GND;
12V for program/erase acceleration:
connect to 12V
VCC
+ 3.3V Power Supply
GND
Ground
PO0~PO6 Parallel data output/input (PO0~PO6 can
be connected to NC in serial mode)
NC No Internal Connection
Note:
1. PO0~PO7 are not provided on 8-LAND SON package.
2. HOLD# is recommended to connect to VCC during
parallel mode.
REV. 1.0, JUL. 15, 2005
2
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BLOCK DIAGRAM
Address
Generator
MX25L3205
Memory Array
SI
CS#, ACC,
WP#,HOLD#
SCLK
Data
Register
SRAM
Buffer
Mode
Logic
State
Machine
Y-Decoder
HV
Generator
Sense
Amplifier
Clock Generator
Output
Buffer
SO
P/N: PM1169
REV. 1.0, JUL. 15, 2005
3
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